HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 943

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which
bits of the channel A break address 31 to 0 (BAA31–BAA0) set in BARA are to be masked.
Bit 3: BAMA2
0
1
Legend: *: Don't care
20.2.5
Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three
conditions—(1) instruction access/operand access, (2) read/write, and (3) operand size—from
among the channel A break conditions.
BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
Initial value:
Initial value:
Break Bus Cycle Register A (BBRA)
R/W:
R/W:
Bit:
Bit:
Bit 1: BAMA1
0
1
0
1
15
—
—
R
R
0
7
0
SZA2
R/W
14
—
R
0
6
0
Bit 0: BAMA0
0
1
0
1
0
1
*
IDA1
R/W
13
—
R
0
5
0
IDA0
Description
All BARA bits are included in break conditions
Lower 10 bits of BARA are masked, and not
included in break conditions
Lower 12 bits of BARA are masked, and not
included in break conditions
All BARA bits are masked, and not included in
break conditions
Lower 16 bits of BARA are masked, and not
included in break conditions
Lower 20 bits of BARA are masked, and not
included in break conditions
Reserved (cannot be set)
R/W
12
—
R
0
4
0
Rev.7.00 Oct. 10, 2008 Page 857 of 1074
Section 20 User Break Controller (UBC)
RWA1
R/W
11
—
R
0
3
0
RWA0
R/W
10
—
R
0
2
0
REJ09B0366-0700
SZA1
R/W
—
R
9
0
1
0
SZA0
R/W
—
R
8
0
0
0