HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 884

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Smart Card Interface
The receive margin in smart card mode can therefore be expressed as shown in the following
equation.
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the
following equation.
When D = 0.5 and F = 0:
(2) Retransfer Operations
Retransfer operations are performed by the SCI in receive mode and transmit mode as described
below.
Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer
operation when the SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is
2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred.
3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to
4. If no error is found when the received parity bit is checked, the receive operation is judged to
5. When a normal frame is received, the pin retains the high-impedance state at the timing for
Rev.7.00 Oct. 10, 2008 Page 798 of 1074
REJ09B0366-0700
automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt
request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit
is sampled.
1.
have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the
RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated.
error signal transmission.
Frame length (L =10)
Absolute deviation of clock frequency
M = (0.5 –
M = (0.5 – 1/2 × 372) × 100% = 49.866%
2N
1
) – (L – 0.5) F –
| D – 0.5 |
N
(1 + F) × 100%