HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 205

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Tag
• V bit (validity bit)
• U bit (dirty bit)
• Data field
• LRU (SH7750R only)
Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached.
The tag is not initialized by a power-on or manual reset.
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5,
Memory-Mapped Cache Configuration (SH7750, SH7750S)). The U bit is initialized to 0 by a
power-on reset, but retains its value in a manual reset.
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be
registered in. The LRU bit is a single bit of each entry, and its value is controlled by hardware.
The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently
accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.
The LRU bits cannot be read or written by software.
Rev.7.00 Oct. 10, 2008 Page 119 of 1074
REJ09B0366-0700
Section 4 Caches