HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 475

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only
be written with 0.
Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2–
DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when
switching from a DACK device to another space, or from a read access to a write access on the
same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual
address transfer, inter-area idle cycles are inserted.
Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits
specify the number of idle cycles between bus cycles to be inserted when switching from external
memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the
same space.
DMAIW2/AnIW2
0
1
DMAIW1/AnIW1
0
1
0
1
DMAIW0/AnIW0
0
1
0
1
0
1
0
1
Rev.7.00 Oct. 10, 2008 Page 389 of 1074
Section 13 Bus State Controller (BSC)
Inserted Idle Cycles
0
1
2
3
6
9
12
15
REJ09B0366-0700
(Initial value)