HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 201

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
• EMODE: Double-sized cache mode bit
• IIX: IC index enable bit
• ICI: IC invalidation bit
• ICE: IC enable bit
• OIX: OC index enable bit*
• ORA: OC RAM enable bit*
• OCI: OC invalidation bit
In the SH7750R, this bit indicates whether the double-sized cache mode is used or not.
This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while
the cache is being used.
0: SH7750/SH7750S-compatible mode*
1: Double-sized cache mode
0: Effective address bits [12:5] used for IC entry selection
1: Effective address bits [25] and [11:5] used for IC entry selection
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
0: Effective address bits [13:5] used for OC entry selection
1: Effective address bits [25] and [12:5] used for OC entry selection
When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be
used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: Normal mode (the entire OC is used as a cache)
1: RAM mode (half of the OC is used as a cache and the other half is used as RAM)
When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always
returns 0 when read.
2
3
1
(initial value)
Rev.7.00 Oct. 10, 2008 Page 115 of 1074
REJ09B0366-0700
Section 4 Caches