HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 593

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
I/O Card Interface Timing: Figures 13.54 and 13.55 show the timing for the PCMCIA I/O card
interface.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set, if the
IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits
in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being
executed, followed automatically by a data access for the remaining 8 bits. Dynamic bus sizing is
also performed in the case of byte-size access to address 2n + 1.
Figure 13.56 shows the basic timing for dynamic bus sizing.
Card 1
on CS5
Card 2
on CS6
The page size can be 1 KB, 4 KB, 64 KB, or 1 MB.
Example of PCMCIA interface mapping
Attribute memory
address space
I/O space 1
I/O space 2
Common
memory 1
Common
memory 2
Virtual
Figure 13.53 PCMCIA Space Allocation
Common memory
Attribute memory
by CS5 wait
by CS6 wait
I/O space
controller
controller
(64 MB)
(64 MB)
(64 MB)
Access
Access
.
.
.
.
.
.
Example of I/O spaces with different cycle times
(less than 1 KB)
1 KB
page
1 KB
page
Rev.7.00 Oct. 10, 2008 Page 507 of 1074
address space
Section 13 Bus State Controller (BSC)
IO 1
IO 2
Virtual
Different virtual pages
mapped to the same
physical page
REJ09B0366-0700
Physical I/O
addresses
IO 1
IO 2

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