UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1335

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
26.3.4 Operation after reset release
2
clock.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
16
/f
Internal oscillation
Internal oscillation
After the reset is released, the main clock starts oscillation and oscillation stabilization time (OSTS register initial value:
WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source
(1) Emergent operation mode
X
V850ES/JG3-H,
V850ES/JG3-H,
) is secured, and the CPU starts program execution.
V850ES/JH3-H
V850ES/JH3-H
Clock monitor
Clock monitor
If an anomaly occurs in the main clock before oscillation stabilization time is secured, WDT2 overflows before
executing the CPU program. At this time, the CPU starts program execution by using the internal oscillation clock
as the source clock.
The CPU operation clock states can be checked with the CPU operation clock status register (CCLS).
Main clock
Main clock
WDT2
WDT2
clock
clock
Operation
Operation
Reset
Reset
stops
stops
Figure 26-5. Operation After Reset Release
Figure 26-6. Operation After Reset Release
Counting of oscillation stabilization time
Counting of oscillation stabilization time
Operation stops
Operation in progress
Operation in progress
Operation stops
CHAPTER 26 RESET FUNCTIONS
WDT overflows
Normal operation (f
Operation in progress (re-count)
(f
CPU
Operation in progress
= internal oscillation clock)
Emergency mode
Page 1335 of 1509
CPU
= Main clock)