UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1509

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
2nd
Edition
Modification of 3.4.4 (2) (d) Data-only RAM (8 KB)
Addition of Caution to 3.4.4 (2) (d) Data-only RAM (8 KB)
Modification of Figure 3-10. Data only RAM (8 KB)
Modification of 3.4.4 (4) External memory area
Modification of 3.4.6 Peripheral I/O registers
Modification of Figure 7-23. (d) TAAn I/O control register 2 (TAAnIOC2)
Modification of Figure 7-27. (d) TAAn I/O control register 2 (TAAnIOC2)
Modification of 7.8 Cascade Connection
Modification of Table 12-1 Configuration of Real-Time Counter
Modification of Figure 12-1. Block Diagram of Real-Time Counter
Addition of 12.3 (17) Prescaler mode register 0 (PRSM0)
Addition of 12.3 (18) Prescaler compare register 0 (PRSCM0)
Addition of Note 2 to 18.4 (2) CSIFn control register 1 (CFnCTL1)
Modification of Table 19-4. Extension Code Bit Definitions
Modification of Figure 19-23. Example of Master to Slave Communication (When 9-
Clock Wait Is Selected for Both Master and Slave)
Modification of Figure 19-24. Example of Slave to Master Communication (When 8-
Clock Wait for Master and 9-Clock Wait for Slave Are Selected)
Modification of Figure 21-1. Block Diagram of USB Function Controller
Addition of 22.3 (7) External DMA request enable register (EXDRQEN)
Modification of Table 25-10. Operating Status in Subclock Operation Mode
Modification of Figure 28-1. Block Diagram of Low-Voltage Detector
Modification of 33.5.1 I/O level
Modification of 33.7.2 (1) (a) Read/write cycle (CLKOUT asynchronous)
Modification of 33.7.2 (1) (b) Read/write cycle (CLKOUT synchronous): In multiplexed
bus mode/separate bus mode
Modification of 33.7.2 (2) (a) CLKOUT asynchronous
33.7.2 (2) (b) CLKOUT synchronous
Modification of 33.7.2 (6) (a) Master mode
Modification of 33.7.2 (6) (b) Slave mode
Modification of 33.8 (10) A/D converter
Addition of APPENDIX E REVISION HISTORY
Description
APPENDIX E REVISION HISTORY
CHAPTER 3
CPU FUNCTION
CHAPTER 7
16-BIT TIMER/EVENT
COUNTER AA (TAA)
CHAPTER 12
REAL-TIME COUNTER
CHAPTER 18
3-WIRE VARIABLE-LENGTH
SERIAL I/O (CSIF)
CHAPTER 19
I2C BUS
CHAPTER 21
USB FUNCTION
CONTROLLER (USBF)
CHAPTER 22
DMA FUNCTION (DMA
CONTROLLER)
CHAPTER 25 STANDBY
FUNCTION
CHAPTER 28
LOW-VOLTAGE DETECTOR
(LVI)
CHAPTER 33 ELECTRICAL
SPECIFICATIONS
APPENDIX E REVISION
HISTORY
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Chapter
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