UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 748

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
17.6.7 UART reception
to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed.
recognized if the RXDCn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive
operation starts, and serial data is saved to the UARTCn receive shift register according to the set baud rate.
the UARTCn receive shift register is written to the UCnRX register. However, if an overrun error (UCnSTR.UCnOVE bit)
occurs, the receive data at this time is not written to the UCnRX register and is discarded.
continues until the reception position of the first stop bit, and INTUCnR is output following reception completion.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The reception wait status is set by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDCn pin is detected and sampling is started at the falling edge. The start bit is
When the reception completion interrupt request signal (INTUCnR) is output upon reception of the stop bit, the data of
Even if a parity error (UCnSTR.UCnPE bit) or a framing error (UCnSTR.UCnFE bit) occurs during reception, reception
Cautions 1. Be sure to read the UCnRX register even when a reception error occurs. If the UCnRX register is
2. The operation during reception is performed assuming that there is only one stop bit. A second
3. When reception is completed, read the UCnRX register after the reception completion interrupt
4. If receive completion processing (INTUCnR signal generation) of UARTCn and the UCnPWR bit =
not read, an overrun error occurs during reception of the next data, and reception errors continue
occurring indefinitely.
stop bit is ignored.
request signal (INTUCnR) has been generated, and clear the UCnPWR or UCnRXE bit to 0. If the
UCnPWR or UCnRXE bit is cleared to 0 before the INTUCnR signal is generated, the read value of
the UCnRX register cannot be guaranteed.
0 or UCnRXE bit = 0 conflict, the INTUCnR signal may be generated in spite of these being no data
stored in the UCnRX register.
To complete reception without waiting for the INTUCnR signal to be generated, be sure to set (1)
the interrupt mask flag (UCnRMK) of the interrupt control register (UCnRIC), clear (0) the UCnPWR
bit or UCnRXE bit, and then clear the interrupt request flag (UCnRIF) of the UCnRIC register.
RXDCn
INTUCnR
UCnRX
Start
bit
D0
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-15. UART Reception
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
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