UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 47

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
2.2
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)
Remark
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The operation states of pins in the various operation modes are described below.
DRST
P10/ANO0, P11/ANO1
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Other port pins
Pin States
2. Operates while alternate functions are operating.
3. The state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer or clock monitor, etc., the state
5. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
6. Operates even in the HALT mode, during DMA operation.
7. In separate bus mode:
8. In separate bus mode
Pin Name
when the power is turned on.
of this pin differs according to the OCDM.OCDM0 bit setting.
In multiplexed bus mode: Undefined
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
Low-level output
High-level output
Input without sampling (not acknowledged)
When Power
Undefined
Pull down
Is Turned
Hi-Z
On
Hi-Z
Note 1
Note 5
Table 2-2. Pin Operation States in Various Modes
Hi-Z
When Power
Pull down
(Other than
Is Turned
Hi-Z
During
Reset
Hi-Z
Hi-Z
On)
4
Note 5
Note
Undefined
Undefined
Operating
Notes 6, 7
Operating
Mode
HALT
H
Held
Held
Held
Note 6
6, 8
−
6
6
Note 2
Notes
Note
Note
Sub-IDLE
Mode
IDLE1,
IDLE2,
Held
Held
Held
Hi-Z
H
−
L
−
Note 2
Mode
STOP
Held
Held
Hi-Z
Hi-Z
H
−
L
−
CHAPTER 2 PIN FUNCTIONS
Note 2
Idle State
Operating
Held
Held
Held
Held
H
−
−
3
Note
Page 47 of 1509
Operating
Operating
Bus Hold
Held
Held
Held
Hi-Z
Hi-Z
−
L