UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 31

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(9) Real-time counter (for watch)
(10) Watchdog timer 2
(11) Serial interface
(12) A/D converter
(13) D/A converter
(14) DMA controller
(15) Key interrupt function
(16) Real-time output function
(17) CRC function
The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768
kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware
counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to
99 years.
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
The V850ES/JG3-H and V850ES/JH3-H include three kinds of serial interfaces (asynchronous serial interface C
(UARTC), 3-wire variable-length serial interface F (CSIF), and an I
(CAN)
UARTC transfers data via the TXDC0 to TXDC2 pins and RXDC0 to RXDC2 pins.
CSIF transfers data via the SOF0 to SOF4 pins, SIF0 to SIF4 pins, and SCKF0 to SCKF4 pins.
In the case of I
CAN
USBF transfers data via the UDMF and UDPF pins.
Note
This 10-bit A/D converter includes 12 analog input pins.
approximation method.
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM, on-chip
peripheral I/O devices, and external memory in response to interrupt requests sent by on-chip peripheral I/O
devices.
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare
register match signal.
A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data
is provided on-chip.
Note
Note
μ
PD70F3770, 70F3771 only
transfers data via the CRXD0
, and a USB function controller (USBF).
2
C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
Note
and CTXD0
Note
pins.
Conversion is performed using the successive
2
C bus interface (I
CHAPTER 1 INTRODUCTION
2
C)), a CAN controller
Page 31 of 1509