UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 820

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
I
(1) IIC shift register n (IICn)
(2) Slave address register n (SVAn)
(3) SO latch
(4) Wakeup controller
(5) Prescaler
(6) Serial clock counter
2
C0n includes the following hardware (n = 0 to 2).
The IICn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both
transmission and reception (n = 0 to 2).
Write and read operations to the IICn register are used to control the actual transmit and receive operations.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
The SVAn register sets local addresses when in slave mode (n = 0 to 2).
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
The SO latch is used to retain the output level of the SDA0n pin (n = 0 to 2).
This circuit generates an interrupt request signal (INTIICn) when the address value set to the SVAn register
matches the received address or when an extension code is received (n = 0 to 2).
This selects the sampling clock to be used.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
Registers
Control registers
Item
Table 19-1. Configuration of I
IIC shift register n (IICn)
Slave address register n (SVAn)
IIC control register n (IICCn)
IIC status register n (IICSn)
IIC flag register n (IICF0n)
IIC clock select register n (IICCLn)
IIC function expansion register n (IICXn)
IIC division clock select registers 0, 1 (OCKS0, OCKS1)
Configuration
2
C0n
CHAPTER 19 I
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2
C BUS