UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 514

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
<1> Count operation start flow
<2> TT0CCR0, TT0CCR1 register
setting change flow (cycle only)
Setting of TT0CCR0 register
Setting of TT0CCR1 register
(TT0CKS0 to TT0CKS2 bits)
Remark
Register initial setting
TT0CCR0 register,
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR1 register
TT0CTL0 register
TT0CE bit = 1
START
n = 0, 1
Figure 9-32. Software Processing Flow in PWM Output Mode (2/2)
Initial setting of these
registers is performed
before setting the
TT0CE bit to 1.
The TT0CKS0 to
TT0CKS2 bits can be
set at the same time
as when counting is
enabled (TT0CE bit = 1).
Writing the same value
(same as preset value of
the TT0CCR1 register)
to the TT0CCR1 register
is necessary only when
the set cycle is changed.
When the counter is
cleared after setting,
the value of the TT0CCRn
register is transferred to the
CCRn buffer register.
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
<3> TT0CCR0, TT0CCR1 register
<4> TT0CCR0, TT0CCR1 register
<5> Count operation stop flow
setting change flow (duty only)
setting change flow (cycle and duty)
Setting of TT0CCR1 register
Setting of TT0CCR0 register
Setting of TT0CCR1 register
TT0CE bit = 0
STOP
Counting is stopped.
Only writing of the TT0CCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register n
is transferred to the CCRn
buffer register.
When the counter is
cleared after setting,
the values of compare
register n are transferred
to the CCRn buffer register
in a batch.
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