78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 12

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78M6612 Data Sheet
1.3 Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to
accurately measure energy. The CE calculations and processes include:
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The CE program resides in Flash memory. Common access to Flash memory by CE and MPU is
controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated Flash space
for the CE program cannot exceed 1024 words (2 KB). The CE program counter begins a pass through
the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is
executed. For proper operation, the code pass must be completed before the multiplexer cycle ends (see
Section 2.2 System Timing
The CE program must begin on a 1 Kbyte boundary of the Flash address. The I/O RAM register
CE_LCTN[4:0] defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is
means of data communication between the two processors.
Table 2
12
located at 1024*CE_LCTN[4:0].
The CE DRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned
time slots are reserved for FIR, RTM, and MPU, respectively, to prevent bus contention for CE DRAM
data access. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM
data, and wait states are inserted as needed, depending on the frequency of CKMPU.
The CE DRAM contains 128 32-bit words. The MPU can read and write the CE DRAM as the primary
Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
CE code is provided by Teridian as a part of the application firmware available. The CE is not
programmable by the user. Measurement algorithms in the CE code can be customized by
Teridian upon request.
shows the CE DRAM addresses allocated to analog inputs from the AFE.
Address (Hex)
Summary).
100C
101C
Table 2: CE DRAM Locations for ADC Results
1000
1004
1008
1010
1014
1018
Name
TEMP
VBAT
VA
VB
IA
IB
–
–
Description
Branch A current
A voltage
Branch B current
B voltage
Not used
Not used
Temperature
Battery voltage
DS_6612_001
Rev. 1.2