78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 35

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS_6612_001
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The
other flags, IE_XFER through IE_WAKE
bit-addressable SFR byte, common practice would be to clear them with a bit operation. This is to be
avoided. The hardware implements bit operations as a byte wide read-modify-write hardware macro. If
an interrupt occurs after the read, but before the write, its flag will be cleared unintentionally. The proper
way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of
the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them.
The AUTOWAKE flag bit is shown in
defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted
to achieve the edge polarity shown in
Rev. 1.2
it is not actually related to an interrupt. This bit is set by hardware when the MPU wakes from a rising
edge on wake timer timeout. The bit is reset by writing a zero.
Each interrupt has its own flag bit, which is set by the interrupt hardware and is reset automatically by the
MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have
their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see
interrupts must be cleared by the MPU software.
processing of any XFER_BUSY or RTC_1SEC interrupt, since both interrupts are edge-triggered.
The external interrupts are connected as shown in
programmable in the MPU via the I3FR and I2FR bits in T2CON
programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4 through 6 are
EX_FWCOL
EX_XFER
EX_RTC
EX_PLL
Name
EX0
EX1
EX2
EX3
EX4
EX5
EX6
Interrupt Enable
When servicing the XFER_BUSY and RTC_1SEC interrupts, special care must be taken to
avoid lock-up conditions: If, for example, the XFER_BUSY interrupt is serviced, control must
not return to the main program without checking the RTC_1SEC
RTC_1SEC interrupt appearing during the XFER_BUSY service routine will disable the
Location
SFR A8[[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
2002[0]
2002[1]
2007[4]
2007[5]
Table 31: Interrupt Enable and Flag Bits
Table 31
Table 31
IE_PLLFALL
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
, are cleared by writing a zero to them. Since these bits are in a
IE_WAKE
IE_XFER
IE_RTC
Name
IEX2
IEX3
IEX4
IEX5
IEX6
IE0
IE1
Interrupt Flag
because it behaves similarly to interrupt flags, even though
.
Table
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
SFR E8[3]
SFR E8[2]
SFR 88[1]
SFR 88[3]
SFRE8[6]
SFRE8[7]
SFRE8[5]
Location
31. The polarity of interrupts 2 and 3 is
. Interrupts 2 and 3 should be
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
FWCOL0 interrupt (int 2)
FWCOL1 interrupt (int 2)
PLL_OK rise interrupt (int 4)
PLL_OK fall interrupt (int 4)
AUTOWAKE flag
Interrupt Description
flag. If this rule is ignored, a
Table
78M6612 Data Sheet
31), and these
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