78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 76

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78M6612 Data Sheet
4.3 I/O RAM Description – Alphabetical Order
Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially
stored in Flash memory and copied to the configuration RAM by the MPU. Some of the more frequently
return zero when they are read.
76
programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the
address range 0x2xxx. Bits with R (read) direction can be read by the MPU. Columns labeled “Rst” and
“Wk” describe the bit values upon reset and wake, respectively. No entry in one of these columns means
the bit is either read-only or is powered by the non-volatile supply and is not initialized. Write-only bits will
Name
ADC_E
BME
CE_E
CE_LCTN[4:0]
CHOP_E[1:0]
CKOUT_E[1:0]
COMP_STAT[0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R3[2:0]*
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_DIR0[7:1]*
Location
2005[3]
2020[6]
2000[4]
20A8[4:0]
2002[5:4]
2004[5,4]
2003[0]
2009[6:4]
200A[2:0]
200A[6:4]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
SFRA2
[7:1]
Table 50: I/O RAM Map – Alphabetical Order
Rst
31
00
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
Wk
31
00
0
–
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
Dir
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Enables ADC and VREF. When disabled, removes bias
current.
Battery Measure Enable. When set, a load current is
immediately applied to the battery and it is connected to
the ADC to be measured on Alternative Mux Cycles. See
MUX_ALT bit.
CE enable.
CE program location. The starting address for the CE
program is 1024*CE_LCTN. CE_LCTN must be defined
before the CE is enabled.
Chop enable for the reference bandgap circuit. The value
of CHOP will change on the rising edge of MUXSYNC
according to the value in CHOP_E:
1
CKTEST Enable. The default is 00.
00-SEG19.
01-CK_FIR (5 MHz Mission, 32 kHz Brownout).
10-Not allowed (reserved for production test).
11-Same as 10.
The status of the power fail comparator for V1.
Connects dedicated I/O pins DIO2 through DIO11 as well
as input pin DIO1 to internal resources. DIO_R3[2:0] is
only available in the 68-pin package. If more than one
input is connected to the same resource, the ‘MULTIPLE’
column below specifies how they are combined.
Programs the direction of pins DIO7- DIO1. DIO3 is only
available on the 68-pin package.
1 indicates output. Ignored if the pin is not configured as
I/O. See DIO_PV and DIO_PW for special option for DIO6
and DIO7 outputs. See DIO_EEX for special option for
DIO4 and DIO5.
00-toggle
except at the mux sync edge at the end of SUMCYCLE.
DIO_Rx
000
001
010
011
100
101
110
111
1
Resource
NONE
Reserved
T0 (Timer0 clock or gate)
T1 (Timer1 clock or gate)
High priority IO interrupt (int0 rising)
Low priority IO interrupt (int1 rising)
High priority IO interrupt (int0
falling)
Low priority IO interrupt (int1 falling)
01-positive
10-reversed
11-toggle
DS_6612_001
Rev. 1.2
Multiple
OR
OR
OR
OR
OR
OR
OR
–