78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 47

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS_6612_001
1.5.10.2 3-Wire EEPROM Interface
A 500 kHz 3-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is
selected with DIO_EEX[1:0] = 10. The same 2-wire EECTRL register is used, except the bits are
reconfigured, as shown in
written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits.
The timing diagrams in
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in
are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the
end of a Read transaction, the EEPROM will be driving SDATA, but will transition to HiZ (high
impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0
and HiZ=0 to take control of SDATA and force it to a low-Z state.
Rev. 1.2
Control
3-0
Bit
7
6
5
4
SDATA output Z
SDATA (output)
EECTRL Byte Written
SCLK (output)
Write -- No HiZ
CNT[3:0]
Name
BUSY (bit)
BUSY
WFR
HiZ
RD
Figure 9
Read/Write
Figure 9: 3-Wire Interface. Write Command, HiZ=0
Table
W
W
W
W
Table 42: EECTRL Bits for 3-Wire Interface
R
42. When EECTRL is written, up to 8 bits from EEDATA are either
through
D7
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be
delayed until a rising edge is seen on the data line. This bit can
be used during the last byte of a Write command to cause the
INT5 interrupt to occur when the EEPROM has finished its
internal write sequence. This bit is ignored if HiZ=0.
Asserted while serial data bus is busy. When the BUSY bit falls,
an INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance
immediately after the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are
0 through 8. If RD=1, CNT bits of data will be read MSB first,
and right justified into the low order bits of EEDATA. If RD=0,
CNT bits will be sent MSB first to EEPROM, shifted out of
EEDATA’s MSB. If CNT is zero, SDATA will simply obey the HiZ
bit.
Figure 13
D6
CNT Cycles (6 shown)
(LoZ)
D5
describe the 3-wire EEPROM interface behavior. All
D4
D3
D2
Figure 9
INT5
78M6612 Data Sheet
through
Figure 13
47