78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 23

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS_6612_001
Rev. 1.2
Register
EEDATA
EECTRL
FLSHCRL
WDI
INTBITS
INT0…INT6
Alternative
Name
Address
0x9E
0xB2
0xE8
0x9F
0xF8
SFR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
Must be re-written for each new Page Erase cycle.
I
I
wishes to write a byte of data to EEPROM, it places the
data in EEDATA and then writes the ‘Transmit’ code to
EECTRL. The write to EECTRL initiates the transmit
sequence. See
description of the command and status bits available for
EECTRL.
Bit 0 (FLSH_PWE): Program Write Enable:
operation (default).
(Flash) @ DPTR.
This bit is automatically reset after each byte written to
Flash. Writes to this bit are inhibited when interrupts are
enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading
of Flash memory and CE program RAM. This bit is reset
on chip reset and may only be set. Attempts to write
zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
The multi-purpose register WDI contains the following
bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
This flag monitors the XFER_BUSY interrupt. It is set by
hardware and must be cleared by the interrupt handler.
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by
hardware and must be cleared by the interrupt handler.
Bit 7 (WD_RST): WD Timer Reset:
Read: Reads the PLL_FALL interrupt flag.
Write 0: Clears the PLL_FALL interrupt flag.
Write 1: Resets the watch dog timer .
Interrupt inputs. The MPU may read these bits to see
the input to external interrupts INT0, INT1, up to INT6.
These bits do not have any memory and are primarily
intended for debug use.
2
2
C EEPROM interface data register.
C EEPROM interface control register. If the MPU
0 – MOVX commands refer to XRAM Space, normal
1 – MOVX @DPTR,A moves A to Program Space
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Only byte operations on the whole WDI
register should be used when writing.
The byte must have all bits set except the
bits that are to be cleared.
Section 1.5.10 EEPROM Interface
Description
78M6612 Data Sheet
for a
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