78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 78

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78M6612 Data Sheet
78
Name
FLSH_ERASE[7:0]
FLSH_MEEN
FLSH_PGADR[6:0]
(FPAG)
FLSH_PWE
FOVRIDE
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_XFER
IE_RTC
IE_WAKE
SFRB7[7:1]
Location
SFR94[7:0]
SFRB2[1]
SFRB2[0]
20FD[4]
SFRE8[2]
SFRE8[3]
SFRE8[6]
SFRE8[7]
SFRE8[0]
SFRE8[1]
SFRE8[5]
Rst
0
0
0
0
0
0
0
0
0
0
0
0
Wk
0
0
0
0
0
0
0
0
0
0
0
–
Dir
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
This bit is automatically reset after each byte written to
Flash. Writes to this bit are inhibited when interrupts are
enabled.
Description
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass
Erase cycle or the Flash Page Erase cycle. Specific
patterns are expected for FLSH_ERASE in order to initiate
the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be
0xAA – Initiate Flash Mass Erase cycle. Must be
Any other pattern written to FLSH_ERASE will have no
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru
127) that will be erased during the Page Erase cycle.
(default = 0x00).
Must be re-written for each new Page Erase cycle.
Program Write Enable
0 – MOVX commands refer to XRAM Space, normal
1 – MOVX @DPTR,A moves A to Program Space (Flash)
Permits the values written by MPU to temporarily override
the values in the fuse register (reserved for production
test).
Interrupt flags for Firmware Collision Interrupt. See Flash
Memory Section for details.
Indicates that the MPU was woken or interrupted (int 4) by
System power becoming available, or more precisely, by
PLL_OK rising. Firmware must write a zero to this bit to
clear it.
Indicates that the MPU has entered BROWNOUT mode
because System power has become unavailable (int 4),
this bit to clear it.
Interrupt flags. These flags monitor the XFER_BUSY
interrupt and the RTC_1SEC interrupt. The flags are set
by hardware and must be cleared by the interrupt handler.
Note that IE6, the interrupt 6 flag bit in the MPU must also
be cleared when either of these interrupts occur.
Indicates that the MPU was woken by the autowake timer.
This bit is typically read by the MPU on bootup. Firmware
must write a zero to this bit to clear it.
@ DPTR.
proceeded by a write to FLSH_PGADR @ SFR
0xB7.
proceeded by a write to FLSH_MEEN @ SFR
0xB2 and the debug (CC) port must be enabled.
effect.
or more precisely, because PLL_OK fell.
Note: this bit will not be set if the part wakes
into BROWNOUT mode because of the
WAKE timer. Firmware must write a zero to
operation (default).
DS_6612_001
Rev. 1.2