78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 28

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78M6612 Data Sheet
Timer/Counter Mode Control Register (TMOD
Bits
when set.
28
Table 18
TMOD[7]
TMOD[3]
TMOD[6]
TMOD[2]
TMOD[5]
TMOD[1]
TMOD[4]
TMOD[0]
M1
0
0
1
1
TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON
Bit
specifies the combinations of operation modes allowed for timer 0 and timer 1.
Note:
overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.
MSB
M0
0
1
0
1
GATE
Symbol
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
Gate
C/T
M1
M0
In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on
Mode 0
Mode 1
Mode 2
Mode 3
Mode
C/T
Timer 1
Function
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,
respectively). When int0 or int1 is high, and TRX bit is set (see TCON
register), a counter is incremented every falling edge on t0 or t1 input pin
Selects Timer or Counter operation. When set to 1, a Counter operation is
performed. When cleared to 0, the corresponding register will function as a
Timer.
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
TMOD
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
TMOD description.
Table 17: Timers/Counters Mode Description
Function
13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1
16-bit Counter/Timer.
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or
TH1, while TL0 or TL1 is incremented every machine cycle. When
TL(x) overflows, a value from TH(x) is copied to TL
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1
and M0 bits are set to 1, Timer 0 acts as two independent 8-bit
Timer/Counters.
M1
description.
Table 16: The TMOD Register
Table 18: Timer Modes
Not allowed
M0
Mode 0
YES
YES
)
register (see
GATE
Not allowed
Timer 1
Mode 1
C/T
YES
YES
Table 15
Timer 0
M1
) start their associated timers
Mode 2
YES
YES
YES
(x).
M0
are held at zero.
LSB
DS_6612_001
Rev. 1.2