78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 52

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

78M6612 Data Sheet
2.2
Figure 16
the two serial output streams. In this example, MUX_DIV[1:0] = 4 and FIR_LEN = 1 (384). The duration of
each MUX frame is 1 + MUX_DIV[1:0] * 2 if FIR_LEN = 0 (288), and 1 + MUX_DIV[1:0] * 3 if FIR_LEN
(384). An ADC conversion will always consume an integer number of CK32 clocks. Followed by the
conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change in
CROSS.
Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of
the CE program, it may continue running until the end of the ADC3 (VB) conversion. CE opcodes are
constructed to ensure that all CE code passes consume exactly the same number of cycles. The result
of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE code is
written to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded
into DRAM is shown in
Figure 16
RTM, consisting of 140 CK cycles, will always finish before the next code pass starts.
52
TMUXOUT/RTM
RTM TIMING
ADC
CE
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
ADC EXECUTION
CE_EXECUTION
Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers
MUX_SYNC
NOTES:
XFER_BUSY
MUX STATE
MUX_SYNC
System Timing Summary
CE_BUSY
CKTEST
CK32
summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and
also shows that the serial RTM data stream begins transmitting at the beginning of state ‘S.’
CK32
RTM
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
FLAG
S
0
0
Figure
1
150
0
30
16.
31
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
Figure 17: RTM Output Format
ADC0
FLAG
450
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
MUX_DIV
0
1
1
Conversions,
30
31
ADC1
ADC MUX Frame
MUX_DIV[1:0]
900
FLAG
2
0
= 01 (4 conversions) is shown
1
30
ADC2
31
1350
FLAG
MAX CK COUNT
3
DS_6612_001
0
1
Rev. 1.2
ADC3
30
180
0
31
= 1
Settle
140
S