78M6612-IMR/F Maxim Integrated Products, 78M6612-IMR/F Datasheet - Page 27

• Manufacturer Part Number: 78M6612-IMR/F
• Description: IC POWER MEASUREMENT AC 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 78M6612-IMR/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS_6612_001
1.4.7 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be
configured for counter or timer operations.
In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12
periods of the MPU clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding
input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO
Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count
rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure
proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
The timers/counters are controlled by the TCON
Timer/Counter Control Register (
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD
and TCON) are used to select the appropriate mode.
Rev. 1.2
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
Bit
MSB
TF1
Symbol
TF1
TR1
TF0
TR0
IE1
IE0
IT1
IT0
TR1
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on
external pin int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level
on input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on
external pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level
on input pin to cause interrupt.
TF0
TCON
Table 15: The
)
TR0
Register
TCON
IE1
Register
IT1
IE0
IT0
78M6612 Data Sheet
LSB
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