TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 124

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

TDA523x
Functional Description
2.4.17
Interrupt Generation Unit
The Interrupt Generation Unit receives all possible interrupts and sets the NINT signal
based on the configuration of the Interrupt Mask register (IM). The Interrupt Status
register is set from the Interrupt Generation Unit, depending on which interrupt occurred.
The polarity of the interrupt that is routed to the NINT/NSTR Pin is defined in the CMC1
register. Please note that during power up and brown out reset, the polarity of the
NINT/NSTR Pin is always as described in
Chapter 2.4.2 Chip
Reset.
A Reset Event has the highest priority. It sets all bits in the Status register to “1” and sets
the Interrupt Pin to “0”. The first interrupt after the Reset Event will clear the Status
register and will set the Interrupt Pin to “1”, even if this interrupt is masked.
A wake up interrupt clears the FsyncA, FsyncB and the complementary wake up Flag. A
Fsync Interrupt clears the EOMA, EOMB, MIDA, MIDB and the complementary Fsync
Flag.
The Interrupt Status register is always cleared after it is read via SPI.
It is not possible to disable the Power On Reset Indicator Interrupt using the Interrupt
Mask register.
IS
Interrupt-Mask
IM
NINTPOL
Interrupt-Signalling
Reset
Data Clock
NINT
from Digital
Receiver
PIN Function
NINTNSTRSEL
NINT/NSTR Pin
Figure 64
Interrupt Generation Unit
Data Sheet
120
Version 4.0, 2007-06-01