TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 41

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TDA5230

Manufacturer Part Number
TDA5230
Description
IC RECEIVER ASK/FSK 28-TSSOP
Manufacturer
Infineon Technologies
Type
Receiverr
Datasheet

Specifications of TDA5230

Package / Case
28-TSSOP
Frequency
433MHz ~ 450MHz, 865MHz ~ 868MHz
Sensitivity
-111dBm
Data Rate - Maximum
20 kbps
Modulation Or Protocol
ASK, FSK
Applications
RKE, TPM, Security Systems
Current - Receiving
8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Operating Frequency
870 MHz
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
SP000076520
TDA5230
TDA5230INTR

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Notes to State Diagram Run Mode Slave:
1.) Wait: Waiting until start up sequencer has completed the power up procedure.
2.) Init: The Receiver will be initialized and the FIFO will be initialized when the SFR
3.) FIFO locked: When the signal fifolk is set, the chip enters this state and remains
4.) Wait: Wait until symbol synchronization is complete. A loss of symbol
5. Wait: Wait until a start of a data packet (frame) is detected. All bits received from
6.) INIT FIFO: The FIFO will be initialized, if the SFR control bit FSINITFIFO is set
7.) Check MID Setup: Check the configuration of the Message ID Unit. Depending on
8.) Init MID Scanning Unit: Initialize the Message ID scanning unit.
9.) Wait: Wait until the Message ID scanning unit has finished the search for a valid
10.)Checking ID Scanning Result: The result of a search for a Message ID is checked.
11.)EOM Check: Incoming data bits are transferred to the FIFO until an EOM is
Data Sheet
control bit INITFIFO is set. Read out the Modulation Type Configuration (ASK or
FSK), which is defined in the SFR control bits AMT/BMT and set the device to the
configured mode. Set the channel to the correct value, which is defined in the
ARFPLL1/BRFPLL1 register.
there until the signal fifolk is reset. In this state, no further data reception is possible
and therefore, no SYNC or FSYNC will be generated, even if a data-packet is present
in the received data stream. (More information on the FIFO behavior can be found in
chapter
synchronization always leads into this state, whatever the current state is. This state
is left only, if symbol-synchronization can be established on the received data stream.
(More information on the synchronization behavior can be found in
Frame
FSYNC until the detection of EOM will be transferred to the FIFO.
the SFR control bit MIDSEN a Message ID scanning is started or not. If no Message
ID scanning is selected, the next state is the state EOM check. Otherwise the
Message ID scanning unit is activated to search for a valid Message ID.
message ID. All incoming data is stored in the FIFO.
If no valid MessageID was found, a search for a new frame is started. Be aware that
all received bits after FSYNC were stored in the FIFO, even if no Message ID was
found. After a successful search for a Message ID , the next state will be EOM check.
detected. The criteria for EOM are defined in the AEOMC/BEOMC register. If the
SFR control bit FIFOLK is set, the signal fifolk will be asserted at EOM. Depending
on the state of fifolk, the next chip state will be FIFO locked or Wait for Symbol
Synchronization.
Synchronization).
Chapter 2.4.15 Data
FIFO).
37
Functional Description
Version 4.0, 2007-06-01
Chapter 2.4.13
TDA523x

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