TRC103 RFM, TRC103 Datasheet
TRC103
Specifications of TRC103
Related parts for TRC103
TRC103 Summary of contents
Page 1
... The TRC103 incorporates a set of low-power states to reduce overall current consumption and extend battery life. The small size and low power consumption of the TRC103 make it ideal for a wide variety of short range radio applications. The TRC103 complies with Directive 2002/95/EC (RoHS). ...
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... Page Configuration Register (PGCFG) .......................................................................................... 39 5.0 Electrical Characteristics ....................................................................................................................... 40 5.1 DC Electrical Characteristics .......................................................................................................... 40 5.2 AC Electrical Characteristics .......................................................................................................... 41 6.0 TRC103 Design In Steps....................................................................................................................... 43 6.1 Determining Frequency Specific Hardware Component Values .................................................... 43 6.1.1 SAW Filters and Related Component Values ....................................................................... 43 6.1.2 Voltage Controlled Oscillator Component Values................................................................. 43 6.2 Determining Configuration Values for FSK Modulation .................................................................. 44 6 ...
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... OOK Transmitter Related Configuration Values ................................................................... 50 6.4 Frequency Synthesizer Channel Programming for FSK Modulation.............................................. 51 6.5 Frequency Synthesizer Channel Programming for OOK Modulation............................................. 52 6.6 TRC103 Data Mode Selection and Configuration .......................................................................... 53 6.6.1 Continuous Data Mode ......................................................................................................... 53 6.6.2 Buffered Data Mode .............................................................................................................. 55 6.6.3 Packet Data Mode................................................................................................................. 57 6 ...
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... PLL LOCKED INDICATOR CONNECT TO GND CONNECT TO GND MAIN 3.3 V SUPPLY VOLTAGE REGULATED SUPPLY FOR ANALOG CIRCUITRY REGULATED SUPPLY FOR DIGITAL CIRCUITRY REGULATED SUPPLY FOR RF POWER AMP CONNECT TO GND RF I/O RF I/O GROUND PAD ON PKG BOTTOM Table 1 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... All major RF communication parameters are programmable and most can be dynamically set. The TRC103 is optimized for very low power consumption (3.3 mA typical in receiver mode). It complies with Euro- pean ETSI, FCC Part 15 and Canadian RSS-210 regulatory standards. Advanced digital features including the TX/RX FIFO and the packet handling data mode significantly reduce the load on the host microcontroller ...
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... TRC103’s SDI, SDO and SCK pins are shown in Figure 2 (component values shown are for 950-960 MHz operation; see Tables 53 and 54 for other frequency bands). On-chip regulators provide stable supply voltages to sensitive blocks and allow the TRC103 to be used with supply voltages from 2.1 to 3.6 V. Most blocks are supplied with a voltage below 1.6 V. ...
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... The host microcontroller is provided with a bit rate clock by the TRC103 to clock the data; using this clock to send the data synchronously is mandatory in FSK configuration and optional in OOK configuration. In buffered mode the data is first written into the 64-byte FIFO via the SPI in- terface ...
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... Receiver The TRC103 is set to receive mode when MCFG00_Chip_Mode[7..5] is set to 011. The receiver is based on a double-conversion architecture. The front-end is composed of an LNA and a mixer whose gains are constant. The mixer down-converts the RF signal to an intermediate frequency which is equal to 1/8 of the LO frequency, which in turn is equal to 8/9 of the RF frequency ...
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... Crystal Oscillator Crystal specifications for the TRC103 reference oscillator are given in Table 3. RFM recommends the XTL1020P crystal, which is specifically designed for use with the TRC103. Note that crystal frequency error will directly trans- late to carrier frequency, bit rate and frequency deviation error. ...
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... F are in MHz the reference crystal frequency and F XTAL . As an example, with a crystal frequency of 12.8 MHz and an LO PLL Loop Filter Components Technical support +1.800.704.6079 is the RF channel RF Name Value Tolerance C8 1000 pF ±10% C9 6800 pF ±10% R1 6.8 kΩ ±5% Table 4 Page TRC103 - 12/15/10 ...
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... Operating Modes The TRC103 has 5 possible chip-level modes. The chip-level mode is set by MCFG00_Chip_Mode[7..5], which is a 3-bit pattern in the configuration register. Table 5 summarizes the chip-level modes: MCFG00_Chip_Mode[7.. Table 6 gives the state of the digital pins for the different chip-level modes and settings: ...
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... The output DATA is valid at the rising edge of DCLK as shown in Figure 8. As shown in Figure 7, the demodulator section includes the FSK demodulator, the OOK demodulator, data and clock recovery and the start pattern detection blocks. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 7 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... The raw output signal from the demodulator may contain jitter and glitches. Data and clock recovery converts the data output of the demodulator into a glitch-free bit-stream DATA and generates a synchronized clock DCLK to be used for sampling the DATA output as shown in Figure 8. DCLK is available on pin IRQ1 when the TRC103 oper- ates in continuous mode. ...
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... Q signal is the inverse of the deviation frequency, which is the low-IF frequency in OOK mode. The RSSI effective dynamic range can be increased adjusting MCFG01_IF_Gain[1..0] for less gain on high signal levels. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. the crystal frequency in kHz, and D the value in MCFG03_Bit_Rate[6..0]. For Figure 9 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... Continuous data mode, but they are used with two additional blocks, the FIFO and SPI. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 10 Figure 11 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... When the TRC103 is in receive mode and MCFG01_Mode [5] bit is set to 1, all of the blocks described above are enabled normal communication frame, the data stream is comprised of preamble bytes, a start pattern and the data. Upon receipt of a matching start pattern the receiver recognizes the start of data, strips off the preamble and start pattern, and stores the data in the FIFO for retrieval by the host microcontroller ...
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... This signal indicates the transmitter FIFO is empty and must be refilled with data to continue transmission. 3.7 IRQ0 and IRQ1 Mapping Two TRC103 outputs are dedicated to host microcontroller interrupts or signaling. The interrupts are IRQ0 and IRQ1 and each have selectable sources. Tables and 11 below summarize the interrupt mapping options. ...
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... IRQ1 Interrupt Source DCLK DCLK DCLK DCLK None (set to 0) FIFOFULL RSSI_IRQ FIFO_Int_Rx CRC_OK FIFOFULL RSSI_IRQ FIFO_Int_Rx IRQ0 Interrupt Source None (set to 0) None (set to 0) FIFO_thresh nFIFOEMPY FIFO_thresh nFIFOEMPY IRQ0 Interrupt Source DCLK DCLK FIFOFULL TX_Stop FIFOFULL TX_Stop Page TRC103 - 12/15/10 ...
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... CLKOUT is enabled, otherwise it is disabled. The output frequency of CLKOUT is defined by the value of the OSCFG1B_Clk_freq[6..2] parameter which gives the frequency divider ratio applied Table 40 for programming details. Note: CLKOUT is disabled when the TRC103 is in sleep mode. If sleep mode is used, the host microcontroller must have provisions to run from its own clock source. ...
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... PKTCFG1C_Pkt_len[6.. value between 65 and 127. The packet format shown in Figure 15 is programma- ble and is made up of the following fields: 1. Preamble 2. Start pattern (network address) 3. Length byte 4. Node address byte (optional) 5. Data bytes 6. Two-byte CRC checksum (optional) www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 14 Figure 15 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... IRQCFG0D_TX_IRQ1[3] bit can then be set to 1, which allows the TX_STOP event to be mapped to IRQ1. TX_STOP signals the last bit to be transmitted has been transferred the modulator. Allow one bit period for this bit to be transmitted before switching out of transmit mode. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... Packet Payload Processing in Transmit and Receive The TRC103 packet handler constructs transmit packets using the payload bytes in the FIFO. In receive, it proc- esses the packets and extracts the payload bytes to the FIFO. Packet processing in transmit and receive are de- tailed below. For transmit, the packet handler adds the following fields and processing to the payload in the FIFO: 1 ...
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... CRC_OK interrupts and the CRC_stat bit are reset when the last byte in the FIFO is read. Note the FIFO can be read in standby mode by setting PGCFG1F_ RnW_FIFO[6] bit standby, reading the last FIFO byte does not clear CRC_OK and the CRC_stat bit. They are reset once the TRC103 is put in receive mode again and a start pattern is detected. ...
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... Another technique called scrambling (whitening) is widely used for randomizing data before radio transmission. The data is scrambled using a random sequence on the transmit side and then descrambled on the receive side using the same sequence. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Figure 16 Figure17 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... The TRC103 packet handler provides a mechanism for scrambling the packet payload. A 9-bit LFSR is used to generate a random sequence. The payload and the 16-bit CRC checksum are XOR’d with this random sequence as shown in Figure 18. The data is descrambled on the receiver side by XORing with the same random se- quence ...
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... The second byte contains the data to be sent in write mode or the new address to read from in read mode. Figure 20 shows the timing diagram for a single byte write sequence to the TRC103 through the SPI configuration interface. Note that nSS_CONFIG must remain low during the transmission of the two bytes (address and data goes high after the first byte, then the next byte will be considered as an address byte ...
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... FIFO or reading from the FIFO. Toggling nSS_DATA indexes the access pointer to each byte in the FIFO in lieu of using explicit addressing. Figure 23 shows the timing diagram for a multiple-byte write sequence to the TRC103 during transmit, and Figure 24 shows the timing for a multi-byte read sequence. www.RFM.com E-mail: info@rfm ...
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... OSCFG1B 0x1A TXCFG1A SYNCFG19 SYNCFG18 SYNCFG17 0x16 SYNCFG16 RXCFG15 RXCFG14 RXCFG13 RXCFG12 RXCFG11 0x10 RXCFG10 IRQCFG0F IRQCFG0E 0x0D IRQCFG0D MCFG0C MCFG0B MCFG0A MCFG09 MCFG08 MCFG07 MCFG06 MCFG05 MCFG04 MCFG03 MCFG02 MCFG01 0x00 MCFG00 Table 12 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... Packet_Hdl_En 2 r/w 1 → Enabled Gain (AGC chain in IF amplifier: 00 → maximum IF gain 01 → -4.5 dB below maximum IF_Gain 1,0 r/w 10 → below maximum 11 → -13.5 dB below maximum www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Table 13 Table 14 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... Table 18 Description RF frequency 1, X counter R1 = 0x77 (01110111) for 915 MHz Table 19 Description RF frequency 1, Y counter P1 = 0x64 (01100100) for 915 MHz Table 20 Technical support +1.800.704.6079 and F are in kHz, DEV XTAL = 12,800 kHz XTAL are in kHz XTAL = 12,800 kHz XTAL Page TRC103 - 12/15/10 ...
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... RX_current 2 r/w 1 → low current (suitable for most applications) 1,0 Not used www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Description RF frequency 1, Z counter S1 = 0x32 (00110010) for 915 MHz Table 21 Table 22 Table 23 Table 24 Table 25 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... FIFOFULL 2 r FIFO full (IRQ source) nFIFOEMPY 1 r low when FIFO empty (IRQ source) FIFO_OVR 0 r/w/c FIFO overrun error. Write this bit to reset it and clear the FIFO. www.RFM.com E-mail: info@rfm.com ©2009-2010 by RF Monolithics, Inc. Table 26 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... Start transmit when FIFO is full (IRQ0 mapped to nFIFOEMPY) 1 → Start transmit when nFIFOEMPY = 1 (IRQ0 mapped to nFIFOEMPY) 0 → Start transmit when bytes equal or greater than FIFO_thresh value (IRQ0 mapped to FIFO_thresh for FIFO_Int_Tx) 1 → Start transmit when nFIFOEMPY = 1 (IRQ0 mapped to nFIFOEMPY) Table 27 Table 28 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... RXCFG13 = 7 OPP Table 30 Technical support +1.800.704.6079 is the 3 dB cutoff frequency of the Butterworth filters in CBW is the upper cutoff frequency of polyphase filters CPP is the center frequency of the OOK polyphase filter in OPP is the XTAL Page TRC103 - 12/15/10 ...
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... RF Monolithics, Inc. Table 31 , for all digital circuitry: REF /(F+1), 0 ≤ F ≤ 255, where F is the register value REF XTAL Table 32 Table 33 Technical support +1.800.704.6079 and F are in MHz REF XTAL = 1. 6 MHz for F = 12.8 MHz REF XTAL Page TRC103 - 12/15/10 ...
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... F = chip rate / 8*π (sets 1 and 1) CAS 01 → chip rate / 8*π (sets 1 and 2) CAS 10 → chip rate / 32*π (sets 2 and 1) CAL 11 → chip rate / 32*π (sets 2 and 2) CAL Table 34 Technical support +1.800.704.6079 is the cutoff frequency for long CAL Page TRC103 - 12/15/10 ...
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... Table 37 Table 38 = 200*(F /12800)*(K + 1)/(F+1), where F CTX XTAL is the crystal frequency in kHz the integer value of TxInterpfilt, XTAL = 200 kHz for F CTX Table 39 Technical support +1.800.704.6079 is the 3 dB bandwidth of the transmitter anti- CTX = 12800 kHz and RXCFG13 = 7 XTAL TRC103 - 12/15/10 Page ...
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... Packet length: the payload size in fixed length mode, the maximum length byte value in variable length mode, and the maximum length byte value in extended variable length packet mode. Pkt_len default: 0000000b Table 41 Description Node address used in filtering received packets in a network. Table 42 Technical support +1.800.704.6079 is the crystal XTAL = F BCO XTAL Page TRC103 - 12/15/10 ...
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... Clear FIFO if CRC fails 1 → Do not clear FIFO Selects read or write FIFO while in standby mode: 0 → Write FIFO 1 → Read FIFO Not used Register Page: 00 → Page 0 selected 01 → Not used 10 → Not used 11 → Not used Table 44 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... V 0.2 0.8 µ µA 0.1 0.9 MAX UNITS 3.7 V +125 ° dBm MAX UNITS 3.6 V +85 °C 0 dBm = 3 Test Condition MCFG0C Bit MCFG0C Bit Power measured at IC output Vil = 0 V Vih = 3 Iol = -1 mA Ioh = +1 mA Page TRC103 - 12/15/10 ...
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... NRZ NRZ at maximum IF gain at minimum IF gain Test Notes differential output including SAW filter insertion loss programmable below carrier power, no modulation no modulation no modulation at 600 kHz offset programmable Page TRC103 - 12/15/10 ...
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... Max clock freq 1 ns SPI_CONFIG setup time - ns SPI_DATA setup time - nSS_CONFIG low to SCK rising edge. ns SCK falling edge to nSS_CONFIG - high. nSS_DATA low to SCK rising edge SCK falling edge to nSS_DATA high. ns nSS_CONFIG rising to falling edge - ns nSS_DATA rising to falling edge - Page TRC103 - 12/15/10 ...
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... SAW Filters and Related Component Values RFM offers a low-loss SAW RF filter for each of the TRC103’s operating bands. The part numbers for these SAW filters and the values of the related tuning components are given in Table 53 (see Figure 2 for component loca- tion). The SAW filters are designed to take advantage of the TRC103’ ...
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... TRC103 to be operated at full rated output power under FCC 15.247 and similar regulations. The TRC103 RF bit rate is set by the value of the byte loaded in MCFG03. For the standard crystal frequency of 12.8 MHz 12800/(64*(D + 1)), with D in the range 127 Where BR is the bit rate in kb/s and D is the integer stored in MCFG03 ...
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... The minimum required deviation for good TRC103 FSK performance is DEV Where F is the deviation in kHz and BR is the bit rate in kb/s. Specific to the TRC103, the minimum recom- DEV mended deviation is ±33 kHz, even at low data rates. F the standard crystal frequency of 12.8 MHz: F ...
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... Determining Transmitter Power Configuration Values European ETSI EN 300 220-1 regulates unlicensed fixed-frequency and FHSS radio operation in the 863- 870 MHz band. A TRC103 transmitter power setting of 10 dBm can be used anywhere in this band, operating on either fixed-frequency or FHSS. Refer to EN 300 220-1 for additional details. ...
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... In the case of frequency hopping, running at a higher bit rate will allow a higher channel hopping rate, which provides more robust operation in a crowded band in trade-off for less range under quiet band conditions. The TRC103 RF bit rate is set by the value of the byte loaded in MCFG03. For the standard crystal frequency of 12.8 MHz 12800/(64*(D + 1)), with the usable range of D for OOK 5 to 127 Where BR is the bit rate in kb/s and D is the integer stored in MCFG03 ...
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... Technical support +1.800.704.6079 is configured with bits 3..0 in RXCFG10 CPP 65 kHz 82 kHz Page TRC103 - 12/15/10 ...
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... OOK Demodulator Related Configuration Values OOK demodulation in the TRC103 is accomplished by comparing the RSSI to a threshold value. An RSSI value greater than the threshold is “sliced” logic 1, and an RSSI value equal or less than the RSSI value is sliced to a logic 0. The TRC103 provides three threshold options - fixed threshold, average-referenced threshold, and peak-referenced threshold ...
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... F average-referenced threshold applications, F mitting a long sequence of bits of the same value, such as the TRC103’s data scrambling or Manchester encod- ing options. The peak-referenced threshold is generated from the RSSI signal using a fast attack, slow decay peak detector emulation. The slicer threshold is immediately set below the peak value of the RSSI signal anytime the RSSI value exceeds the threshold ...
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... MCFG08 S1 MCFG09 R2 MCFG0A P2 MCFG0B S2 Table 63 MCFG00 bits 4..3 Band 10 863 - 870 MHz 00 902 - 915 MHz 01 915 - 928 MHz 10 950 - 960 MHz 11 not used Table 64 Technical support +1.800.704.6079 OOK Rise/Fall Time 2.5/2 µs 5/3 µs 10/6 µs 20/10 µs TRC103 - 12/15/10 Page ...
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... MHz is normally used, which must match the receiver low IF fre- Register Divider Parameter MCFG06 MCFG07 MCFG08 MCFG09 MCFG0A MCFG0B Table 66 MCFG00 bits 4..3 10 863 - 870 MHz 00 902 - 915 MHz 01 915 - 928 MHz 10 950 - 960 MHz 11 Table 67 Technical support +1.800.704.6079 955.0 MHz 01 10 100 119 Band not used Page TRC103 - 12/15/10 ...
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... R has a value in the range 169 ues and R for OOK transmit operation on several common frequencies are given in Table 69 for a 0.1 MHz F . Software for determining P, S and R values is provided with the TRC103 development kit. IF2 6.6 TRC103 Data Mode Selection and Configuration The TRC103 supports three data modes: continuous, buffered and packet ...
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... As shown in Figure 19, two interrupt (control) outputs, IRQ0 and IRQ1, are provided by the TRC103 to coordinate data flow to and from the host microcontroller. In Continuous data mode, one of two signals can be mapped to IRQ0. This mapping is configured in register IRQCFG0D. Bits 7..6 select the signal for IRQ0 in the receive mode. The mapping options for Continuous data mode are summarized in Table 72, where X denotes a don’ ...
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... In Buffered data mode operation, the transmitted and received data bits pass through the SPI port in groups of 8 bits to the internal TRC103 FIFO. Bits flow from the FIFO to the modulator for transmission and are loaded into the FIFO as data is received. As discussed in Sections 3.10 and 3.11, the SPI port can address the data FIFO or the configuration registers ...
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... RF signal ≥ RSSI threshold signal < RSSI Threshold 1 PLL not locked 0 1 PLL_LOCK signal disabled (bit 1 above), Pin 23 set high 0 PLL_LOCK signal enabled Table 74 MCFG05 bits 7..6 FIFO Length Table 75 Technical support +1.800.704.6079 FIFO Control PLL locked 16 bytes 32 bytes 48 bytes 64 bytes Page TRC103 - 12/15/10 ...
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... The host microcontroller can use a countdown on the length byte or detection of the end-of-message byte to determine when all of the message data has been retrieved. 22. As soon as all the message has been retrieved, switch the TRC103 to standby mode by setting MCFG00 bits 7..5 to 001. 23. From standby mode, enter another transmit cycle as outlined in steps 12 through 15, or enter another re- ceive cycle as outlined in steps 16 through 23 ...
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... Start transmission if nFIFOEMPY = 1 (not empty) 0 Disable RSSI interrupt (bit 2) 1 Enable RSSI interrupt (bit 2) RF signal ≥ RSSI threshold signal < RSSI Threshold Table 77 Technical support +1.800.704.6079 Source Data_Rdy (CRC OK) nFIFOEMPY if Start_Full = 1 CRC_OK FIFOFULL RSSI_IRQ FIFO_Int_Rx (FIFO_thres) FIFOFULL TX_STOP FIFO Control Page TRC103 - 12/15/10 ...
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... PKTCFG1E bits 6..5 Preamble Length 00 1 byte 01 2 bytes 10 3 bytes 11 4 bytes Table 79 Node Address Filtering 00 no filtering 01 only node address accepted 10 node address and 0x00 accepted 11 node address, 0x00 and 0xFF accepted Table 80 Technical support +1.800.704.6079 Page TRC103 - 12/15/10 ...
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... If set to 1, the FIFO data is preserved when the CRC calcula- tion shows an error. PKTCFG1F bit 6 allows the FIFO to be written to or read when the TRC103 is in standby mode. Setting this bit to 0 allows the FIFO to be written and setting this bit to 1 allows read. ...
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... Sensor networks that monitor parameters that change relatively slowly, such as air and soil temperature in agricultural settings, only need to transmit updates a few times an hour. At room temperature the TRC103 draws a maximum of 1 µA in sleep mode, with a typical value of 100 nA. To achieve minimum sleep mode current, nSS_CONFIG (Pin 14), SDI (Pin 17) and SCK (Pin 18) must be held logic low, while nSS_DATA (Pin 15) must be held logic high ...
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... PLL will lock in less than 0.5 ms. PLL lock can be monitored on Pin 23 of the TRC103. The radio can then be switched to either transmit or receive mode. When switching from any other mode back to sleep, the TRC103 will drop to its sleep mode current in less than 1 ms. ...
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... Page TRC103 - 12/15/10 ...
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... Table 83 Technical support +1.800.704.6079 inches minimum nominal maximum 0.199 0.207 0.215 0.199 0.207 0.215 - 13.0 - 0.039 0.043 0.047 0.311 0.315 0.319 - 0.488 - 0.461 0.472 0.484 Page TRC103 - 12/15/10 ...