TRC103 RFM, TRC103 Datasheet - Page 17

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

Figure 12
3.6 Transmitting in Continuous or Buffered Data Modes
The transmitter operates in Continuous data mode when the MCFG01_Mode [5] bit is set to 0. Bit clock DCLK is
available on pin IRQ1. Bits are clocked into the transmitter on the rising edge of this clock. Data must be stable
2 µs before the rising edge of DCLK and must be held for 2 µs following the rising edge of this clock (T
). To
SUDATA
meet this requirement, data can be changed on the falling edge of DCLK. In FSK mode DCLK must be used but is
optional in OOK mode.
The transmitter operates in Buffered data mode when the MCFG01_Mode [5] bit is set to 1. Data to be transmit-
ted is written to the 64-byte FIFO through the SPI interface. FIFO data is loaded byte-by-byte into a shift register
which then transfers the data bit-by-bit to the modulator. FIFO operation in transmit mode is similar to receive
mode. Transmission can start immediately after the first byte of data is written into the FIFO or when the FIFO is
full, as determined by the IRQCFG0E_Start_Full[4] bit setting. If the transmit FIFO is full, the interrupt signal
IRQCFG0D_ FIFOFULL[2] is asserted on pin IRQ1. If data is written into the FIFO while it is full, the flag
IRQCFG0D_FIFO_OVR[0] will be set to 1 and the previous FIFO contents will be overwritten. The IRQCFG0D_
FIFO_OVR[0] flag is cleared by writing a 1 to it. At the same time the contents of the FIFO are cleared. Once the
last data byte in the FIFO is loaded into the shift register driving the transmitter modulator, the flag IRQCFG0D_
nFIFOEMPY[1] is set to 0 on pin IRQ0. If new data is not written to the FIFO and the last bit has been transferred
to the modulator, the IRQCFG0E_TX_ STOP[5] bit goes high as the modulator starts to send the last bit. The
transmitter must remain on one bit period after TX_STOP to transmit the last bit. If the transmitter is switched off
(switched to another mode), the transmission stops immediately even if there is still data in the shift register. In
transmit mode the two interrupt signals are IRQ0 and IRQ1. IRQ1 is mapped to IRQCFG0D_FIFOFULL[2] signal
indicating that the transmission FIFO is full when IRQCFG0D_TX_IRQ1[3] is set to 0, or to IRQCFG0E_TX_
STOP[5] when IRQCFG0D_ TX_IRQ1[3] is set to 1. IRQ0 is mapped to the IRQCFG0D_nFIFOEMPY[1] signal.
This signal indicates the transmitter FIFO is empty and must be refilled with data to continue transmission.
3.7 IRQ0 and IRQ1 Mapping
Two TRC103 outputs are dedicated to host microcontroller interrupts or signaling. The interrupts are IRQ0 and
IRQ1 and each have selectable sources. Tables 8, 9, 10 and 11 below summarize the interrupt mapping options.
These interrupts are especially useful in Continuous or Buffered data mode operation.
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TRC103 - 12/15/10