TRC103 RFM, TRC103 Datasheet - Page 14

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

Data and clock recovery is enabled by default. It is controlled by RXCFG12_DCLK_Dis[6]. If data and clock re-
covery is disabled, the output of the demodulator is directed to DATA and the DCLK output (IRQ1 Pin in continu-
ous mode) is set to 0.
The received bit rate is defined by the value of the MCFG03_Bit_Rate[6..0] configuration register, and is calcu-
lated as follows:
BR = F
/(64*(D + 1)), with D in the range of 0 to 127
XTAL
with BR the bit rate in kb/s, F
the crystal frequency in kHz, and D the value in MCFG03_Bit_Rate[6..0]. For
XTAL
example, using a 12.8 MHz crystal (12,800 kHz), the bit rate is 25 kb/s when D = 7.
3.3 Continuous Mode Start Pattern Recognition
Start pattern detection (recognition) is activated by setting the RXCFG12_Recog[5] bit to 1. The demodulated
signal is compared with a pattern stored in the SYNCFG registers. The Start Pattern Detect (PATTERN) signal,
mapped to output pin IRQ0, is driven by the output of this comparator and is synchronized by DCLK. It is set to 1
when a start pattern match is detected, otherwise it is set to 0. The Start Pattern Detect output is updated at the
rising edge of DCLK. The number of bytes used for comparison is defined in the RXCFG12_Pat_sz[4..3] register
and the number of tolerated bit errors for the pattern detection is defined in the RXCFG12_Ptol[2..1] register.
Figure 9 illustrates the pattern detection process.
Figure 9
Note that start pattern detection is enabled only if data and clock recovery is enabled.
3.4 RSSI
The received signal strength is measured in the amplifier chains behind the second mixers. Each amplifier chain
is composed of 11 amplifiers each having a gain of 6 dB and an intermediate output at 3 dB. By monitoring the
two outputs of each stage, an estimation of the signal strength with a resolution of 3 dB and a dynamic range of
63 dB is obtained without IF gain compensation. This estimation is performed 16 times over a period of the I and
Q signals and the 16 samples are averaged to obtain a final RSSI value with a 0.5 dB step. The period of the I
and Q signal is the inverse of the deviation frequency, which is the low-IF frequency in OOK mode. The RSSI
effective dynamic range can be increased to 70 dB by adjusting MCFG01_IF_Gain[1..0] for less gain on high
signal levels.
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TRC103 - 12/15/10