TRC103 RFM, TRC103 Datasheet - Page 11

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

3.0 Operating Modes
The TRC103 has 5 possible chip-level modes. The chip-level mode is set by MCFG00_Chip_Mode[7..5], which
is a 3-bit pattern in the configuration register. Table 5 summarizes the chip-level modes:
Table 6 gives the state of the digital pins for the different chip-level modes and settings:
The TRC103 transmitter and receiver sections support three data handling modes of operation:
The Buffered and Packet data modes allow the host microcontroller overhead to be significantly reduced. The
DATA pin is bidirectional and is used in both transmit and receive modes. In receive mode, DATA represents the
demodulated received data. In transmit mode, input data is applied to this pin.
www.RFM.com
©2009-2010 by RF Monolithics, Inc.
•
•
•
Continuous mode: each bit transmitted or received is accessed directly at the DATA input/output pin.
Buffered mode: a 64-byte FIFO is used to store each data byte transmitted or received. This data is writ-
ten to and read from the FIFO through the SPI bus.
Packet handling mode: in addition to using the FIFO, this data mode builds the complete packet in
transmit mode and extracts the useful data from the packet in receive mode. The packet includes a pre-
amble, a start pattern (sync pattern), an optional node address and length byte and the data. Packet data
mode can also be configured to perform additional operations like CRC error detection and DC-balanced
Manchester encoding or data scrambling.
E-mail:
MCFG00_Chip_Mode[7..5]
[e-mail]
PIN Function
nSS_CONFIG*
nSS_DATA*
IRQ0
IRQ1
DATA
CLKOUT
SDO**
SDI
SCK
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
I = Input, O = Output, TRI = High impedance
*nSS_CONFIG has priority OVER nSS_DATA
**SDO is an output if nSS_CONFIG = 0 and/or nSS_DATA = 0
Sleep
Mode
TRI/O
TRI
TRI
TRI
TRI
I
I
I
I
Technical support +1.800.704.6079
Chip-level Mode
Synthesizer
Transmit
Standby
Receive
Sleep
Standby
TRI/O
Mode
TRI
O
O
O
I
I
I
I
Table 5
Table 6
Synthesizer
Enabled Functions
None
Crystal oscillator
Crystal and frequency synthesizer
Crystal, frequency synthesizer and receiver
Crystal, frequency synthesizer and transmitter
Mode
TRI/O
TRI
O
O
O
I
I
I
I
Receive
Mode
TRI/O
O
O
O
O
I
I
I
I
Transmit
TRI/O
Mode
O
O
O
I
I
I
I
I
TRC103 - 12/15/10
Page 11 of 64