TRC103 RFM, TRC103 Datasheet - Page 55

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

The motivation for disabling clocking when transmitting or receiving OOK is that non-standard bit rates can be
used. However, the host microcontroller must handle the data and clock recovery functions. When using continu-
ous mode with or without clocking enabled, data should be encoded to provide DC-balance (same number
of 1 and 0 bits) and limited run lengths of the same bit value. Manchester encoding, 8-to-12 bit symbolizing or
scrambling must be applied to the data before transmitting and removed after receiving to achieve good RF
transmission performance. The preamble, start pattern and error checking bits must also be generated by the
host microcontroller to establish robust data communications.
6.6.2 Buffered Data Mode
In Buffered data mode operation, the transmitted and received data bits pass through the SPI port in groups of
8 bits to the internal TRC103 FIFO. Bits flow from the FIFO to the modulator for transmission and are loaded into
the FIFO as data is received. As discussed in Sections 3.10 and 3.11, the SPI port can address the data FIFO or
the configuration registers. Asserting a logic low on the nSS_DATA input addresses the FIFO, and asserting a
logic low on the nSS_CONFIG addresses the configuration registers. If both of these inputs are asserted,
nSS_CONFIG will override nSS_DATA. The TRC103 acts as an SPI slave and receives clocking from its host
microcontroller. SPI read/write details are provided in Sections 3.10 and 3.11. As shown in Figure 19, two inter-
rupt (control) outputs, IRQ0 and IRQ1, are provided by the TRC103 to coordinate SPI data flow to and from the
host microcontroller. One to four signals can selected or mapped to each interrupt output. This mapping is config-
ured in register IRQCFG0D. Bits 7..6 select the signal for IRQ0 in the receive mode, with IRQ0 hard coded to
nFIFOEMPY in transmit mode. Bits 5..4 select the signal for IRQ1 in the receive mode. Bit 3 selects the IRQ1 sig-
nal in transmit mode. The mapping options for Buffered data mode are summarized in Table 73:
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IRQCFG0D bits
7..6
7..6
7..6
7..6
5..4
5..4
5..4
5..4
3
3
3
[e-mail]
IRQCFG0D bits
Cfg
00
01
10
11
00
01
10
11
X
0
1
7..6
7..6
5..4
3
3
State
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
TX
00, 1X
Technical support +1.800.704.6079
Cfg
XX
01
X
X
IRQ
0
0
0
0
1
1
1
1
0
1
1
State
RX
RX
RX
TX
TX
Write_byte (high pulse when received byte written to FIFO)
Table 72
Table 73
IRQ
0
0
0
1
1
nFIFOEMPY (low when FIFO is empty)
nFIFOEMPY (low when FIFO is empty)
Start Pattern Detect
Start Pattern Detect
None (set to 0)
None (set to 0)
FIFO_Int_Rx
None (set to 0)
FIFOFULL
FIFOFULL
RSSI_IRQ
TX_STOP
RSSI_IRQ
Source
Source
DCLK
DCLK
TRC103 - 12/15/10
Page 55 of 64