TRC103 RFM, TRC103 Datasheet - Page 2

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

1.0 Pin Configuration..................................................................................................................................... 4
2.0 Functional Description............................................................................................................................. 5
3.0 Operating Modes................................................................................................................................... 11
4.0 Configuration Register Memory Map .................................................................................................... 28
5.0 Electrical Characteristics ....................................................................................................................... 40
6.0 TRC103 Design In Steps....................................................................................................................... 43
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1.1 Pin Description.................................................................................................................................. 4
2.1 RF Port.............................................................................................................................................. 7
2.2 Transmitter........................................................................................................................................ 7
2.3 Receiver............................................................................................................................................ 8
2.4 Crystal Oscillator............................................................................................................................... 9
2.5 Frequency Synthesizer ................................................................................................................... 10
2.6 PLL Loop Filter................................................................................................................................ 10
3.1 Receiving in Continuous Mode ....................................................................................................... 12
3.2 Continuous Mode Data and Clock Recovery.................................................................................. 13
3.3 Continuous Mode Start Pattern Recognition .................................................................................. 14
3.4 RSSI................................................................................................................................................ 14
3.5 Receiving in Buffered Data Mode ................................................................................................... 15
3.6 Transmitting in Continuous or Buffered Data Modes ..................................................................... 17
3.7 IRQ0 and IRQ1 Mapping ................................................................................................................ 17
3.8 Buffered Clock Output .................................................................................................................... 19
3.9 Packet Data Modes ........................................................................................................................ 19
3.10 SPI Configuration Interface........................................................................................................... 25
3.11 SPI Data FIFO Interface ............................................................................................................... 27
4.1 Main Configuration Registers (MCFG) ........................................................................................... 29
4.2 Interrupt Configuration Registers (IRQCFG) .................................................................................. 32
4.3 Receiver Configuration Registers (RXCFG)................................................................................... 34
4.4 Start Pattern Configuration Registers (SYNCFG) .......................................................................... 37
4.5 Transmitter Configuration Registers (TXCFG) ............................................................................... 37
4.6 Oscillator Configuration Register (OSCFG).................................................................................... 38
4.7 Packet Handler Configuration Registers (PKTCFG) ...................................................................... 38
4.8 Page Configuration Register (PGCFG) .......................................................................................... 39
5.1 DC Electrical Characteristics .......................................................................................................... 40
5.2 AC Electrical Characteristics .......................................................................................................... 41
6.1 Determining Frequency Specific Hardware Component Values .................................................... 43
6.2 Determining Configuration Values for FSK Modulation .................................................................. 44
3.9.1 Fixed Length Packet Mode ................................................................................................... 19
3.9.2 Variable Length Packet Mode ............................................................................................... 20
3.9.3 Extended Variable Length Packet Mode............................................................................... 20
3.9.4 Packet Payload Processing in Transmit and Receive .......................................................... 22
3.9.5 Packet Filtering...................................................................................................................... 23
3.9.6 Cyclic Redundancy Check .................................................................................................... 23
3.9.7 Manchester Encoding ........................................................................................................... 24
3.9.8 DC-Balanced Scrambling ...................................................................................................... 24
6.1.1 SAW Filters and Related Component Values ....................................................................... 43
6.1.2 Voltage Controlled Oscillator Component Values................................................................. 43
6.2.1 Bit Rate Related FSK Configuration Values ......................................................................... 44
6.2.2 Determining Transmitter Power Configuration Values.......................................................... 46
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Table of Contents
TRC103 - 12/15/10
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