TRC103 RFM, TRC103 Datasheet - Page 56

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

In addition, IRQCFG0E allows several internal FIFO interrupts to be configured. These are summarized in Table
74 below:
MCFG05 bits 7..6 set the length of the FIFO as shown in Table 75:
The integer value of MCFG05 bits 5..0 plus 1 sets the FIFO interrupt threshold. When receiving in Buffered data
mode, FIFO_Int_Rx is triggered when the number of bytes in the FIFO is equal to or greater than the threshold.
The FIFO threshold facilitates sending and receiving messages longer than the chosen FIFO length, by signaling
when additional bytes should be added to the FIFO during a packet transmission and retrieved from the FIFO dur-
ing a packet reception. Two additional interrupts, nFIFOEMPY and FIFOFULL provide signaling that a packet
transmission is complete or a full packet has been received respectively.
The following is a typical Buffered data mode operating scenario. There are many other ways to configure this
very flexible data mode.
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1. Switch to standby mode by setting MCFG00 bits 7..5 to 001.
2. Set the FIFO to a suitable size for the application in MCFG05 bits 7..6.
3. Set the start pattern length in RXCFG12 bits 4..3.
4. Load the start pattern in registers SYNCFG16 up through SYNCFG19 as required.
5. Set IRQCFG0E bit 7 to 0. In receive, the FIFO will start filling when a start pattern is detected.
6. Set IRQCFG0D bit 7..6 to 01. In receive, IRQ0 will flag each time a byte is ready to be retrieved.
7. Set IRQCFG0D bit 5..4 to 00. IRQ1 signaling will not be required in receive mode.
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IRQCFG0E bits
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
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Cfg
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
MCFG05 bits 7..6
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PLL_LOCK signal disabled (bit 1 above), Pin 23 set high
00
01
10
11
Stop filling FIFO (if bit 7 is 0, this is start pattern detect)
Start transmission if nFIFOEMPY = 1 (not empty)
Start FIFO fill when start pattern detected
Table 74
Table 75
Transmitting all pending bits in FIFO
Start transmission when FIFO full
Disable RSSI interrupt (bit 2)
Enable RSSI interrupt (bit 2)
RF signal < RSSI Threshold
RF signal ≥ RSSI threshold
All bits in FIFO transmitted
PLL_LOCK signal enabled
Control FIFO with bit 6
FIFO Length
Start filling FIFO
PLL not locked
FIFO Control
16 bytes
32 bytes
48 bytes
64 bytes
PLL locked
TRC103 - 12/15/10
Page 56 of 64