TRC103 RFM, TRC103 Datasheet - Page 58

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

The SPI interface is used with Packet data mode as with Buffered data mode. IRQ0 and IRQ1 mapping is config-
ured in register IRQCFG0D. Bits 7..6 select the signal for IRQ0 in the receive mode. In transmit mode, IRQ0
mapping is set by IRQCFG0E bit 4. IRQCFG0D bits 5..4 select the signal for IRQ1 in the receive mode. Bit 3 se-
lects the IRQ1 signal in transmit mode. The mapping options for Packet data mode are summarized in Table 76
below:
In addition, IRQCFG0E allows several internal FIFO interrupts to be configured. These are summarized in Table
77 below:
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Generation of a 16-bit error detection CRC
Optional 1-byte node address and/or 1-byte length address
Recognition of start pattern in receive mode
Automatic removal of preamble and start pattern in receive mode (payload only in FIFO)
Flagging of received packets with errors or flagging and discard of packets with errors
Filtering of received packets based on address byte - address match only, address byte plus 0x00
broadcast address or address byte plus 0x00 and 0xFF broadcast addresses
New IRQ0 and IRQ1 mapping options
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IRQCFG0D bits
IRQCFG0E bits
7..6
7..6
7..6
7..6
5..4
5..4
5..4
5..4
3
3
3
3
7
7
6
6
5
5
4
4
3
3
2
2
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Cfg
Cfg
00
01
10
11
00
01
10
11
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
0
State
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
TX
TX
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IRQ
Stop filling FIFO (if bit 7 is 0, this is Start Pattern Detect)
0
0
0
0
0
1
1
1
1
0
1
1
Start transmission when FIFO at or above threshold0
Start transmission if nFIFOEMPY = 1 (not empty)
Start FIFO fill when Start Pattern detected
Write_byte (high pulse when received byte written to FIFO)
Table 76
Table 77
Transmitting all pending bits in FIFO
Disable RSSI interrupt (bit 2)
Enable RSSI interrupt (bit 2)
RF signal < RSSI Threshold
RF signal ≥ RSSI threshold
All bits in FIFO transmitted
or Node Address Match (ADDRS_cmp = 1)
FIFO_Int_Tx (FIFO_thres) if Start_Full = 0
Control FIFO with bit 6
nFIFOEMPY (low when FIFO is empty)
Start Pattern Detect (ADDRS_cmp = 0)
Start filling FIFO
FIFO Control
nFIFOEMPY if Start_Full = 1
FIFO_Int_Rx (FIFO_thres)
Data_Rdy (CRC OK)
FIFOFULL
FIFOFULL
RSSI_IRQ
TX_STOP
CRC_OK
Source
TRC103 - 12/15/10
Page 58 of 64