TRC103 RFM, TRC103 Datasheet - Page 21

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

In extended variable length packet mode, the length of the rest of the payload is given by the first byte written to
the FIFO. The length byte itself is not included in this count. There are a number of ways to use the extended
variable length packet capability. The most common way is outlined below:
1. Set PKTCFG1C_Pkt_len[6..0] to a value between 65 (0x41) and 127 (0x7F). This sets the maximum allowed
payload in extended packet mode. Any received packet having a value in the length byte greater than this maxi-
mum is discarded.
2. Set PKTCFG1E_Pkt_mode[7] to 1 for variable length packet mode operation. Set the PKTCFG1E_ Pre-
amb_len[6..5] bits to 10 or 11 for a minimum of 3 to 4 preamble bytes. Set the PKTCFG1E_CRC_En[3] bit to 1
to enable CRC processing. Set the PKTCFG1E_Pkt_ADDRS_cmp[2..1] bits as required. Clear the PKTCFG1E_
CRC_stat[0] bit by writing a 1 to it.
3. Set MCFG05_FIFO_depth[7..6] bits to 11 for a 64-byte FIFO length.
4. Set the MCFG05_FIFO_thresh[5..0] to approximately 31(0x1F). This sets the threshold to 32, near the mid
point of the FIFO. Provided the host microcontroller is relatively fast (usual case), this setting can be used for
monitoring the FIFO in both transmit and receive. If the host microcontroller is relatively slow, set the threshold to
a value lower than 31 for receive, and higher than 31 for transmit.
5. Set the IRQCFG0D_RX_IRQ1[5..4] bits to 11. This maps FIFO_Int_Rx interrupt to IRQ1, which trips when the
number of received bytes in the FIFO is equal to or greater than the value in MCFG05_FIFO_thresh. IRQ1 will
then signal received bytes must be retrieved. If received bytes are not retrieved before the FIFO completely fills,
data will be lost.
6. Set the IRQCFG0E_Start_Full[4] bit to 0. This causes a transmission to start when the number of transmit
bytes in the FIFO is equal to or greater than the value in MCFG05_FIFO_thresh. Also, the FIFO_Int_Tx interrupt
is mapped to IRQ0 in transmit mode, and is set when the number of bytes in the FIFO is equal to or less than the
value in MCFG05_FIFO_thresh. IRQ0 will then signal more bytes can be added to the FIFO. If more message
bytes are not added in time, the transmission will cease prematurely and data will be lost. Likewise, if more bytes
are sent to the FIFO than it has room for, data will be lost.
7. When receiving an extended variable length packet, monitor IRQ1. When IRQ1 trips, clock out some of the re-
ceived bytes from the FIFO (leave at least one byte in the FIFO). Repeat the partial packet retrieval each time
IRQ1 triggers. The first byte received is the number of message bytes, and can be used to tell when the last mes-
sage byte has been retrieved. When it is determined that the remaining message bytes will not overflow the FIFO,
the IRQCFG0D_RX_IRQ1[5..4] bits can be set to 00, which maps CRC_OK to IRQ1. After the CRC is checked,
the final bytes can be read from the FIFO and the IRQCFG0D_RX_IRQ1[5..4] bits can be reset to 11 to track
FIFO_Int_Rx when the next packet is received. Note that CRC mapping to IRQ1 is not required if the CRC state is
read from the PKTCFG1E_ CRC_stat[0] bit prior to reading the final FIFO bytes.
8. When transmitting an extended variable length packet, begin filling the FIFO until IRQ0 trips, indicating the
FIFO is half full. Add up to 32 bytes to the FIFO (64 - (MCFG05_ FIFO_thresh +1)) when IRQ0 resets. Repeat the
partial packet loading each time IRQ0 resets until all bytes to be transmitted have been clocked in. The
IRQCFG0D_TX_IRQ1[3] bit can then be set to 1, which allows the TX_STOP event to be mapped to IRQ1.
TX_STOP signals the last bit to be transmitted has been transferred the modulator. Allow one bit period for this bit
to be transmitted before switching out of transmit mode.
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TRC103 - 12/15/10