TRC103 RFM, TRC103 Datasheet - Page 33

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

0x0E - IRQCFG0E [default 0x01]
0x0F - IRQCFG0F [default 0x00]
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Name
Start_Fill
Start_Det
TX_STOP
Start_Full
RSSI_Int
SIG_DETECT
PLL_LOCK_EN
Name
RSSI_thld
PLL_LOCK_ST
E-mail:
Bits
Bits
7..0
7
6
5
4
3
2
1
0
[e-mail]
r/w/c
r/w/c
r/w/c
R/W
R/W
r/w
r/w
r/w
r/w
r/w
r
Description
FIFO fill mode selection:
0 → FIFO starts filling when start pattern is detected
1 → FIFO fills as long as Start_Det is 1
Start of FIFO fill:
Start_Fill = 0, goes high when start pattern detected. Write a 1 to reset this bit and
start pattern detect.
Start_Fill = 1
Transmit state:
Buffered data mode:
Packet data mode:
Enables SIG_DETECT:
0 → Disable interrupt
1→ Enable interrupt
Detects a signal above the RSSI_thld:
0 → Signal lower than threshold
1 → Signal equal or greater than the RSSI_thld level
This bit must be cleared by writing a 1 to its location.
Detects the PLL lock status:
0 → PLL not locked
1 → PLL locked
This bit latches high each time the PLL locks and must be cleared by writing a 1 to its location.
Enables the PLL_LOCK signal on Pin 23
0 → PLL_LOCK signal disabled, Pin 23 set high
1 → PLL_LOCK signal enabled
Description
RSSI threshold level for interrupt.
RSSI_thld default is 0x00
0 → Stop filling FIFO
1 → Start filling FIFO
0 → Transferring bits to the TX modulator
1 → Last bit transferred to the TX modulator
0 → Start transmit when FIFO is full (IRQ0 mapped to nFIFOEMPY)
1 → Start transmit when nFIFOEMPY = 1 (IRQ0 mapped to nFIFOEMPY)
0 → Start transmit when bytes equal or greater than FIFO_thresh value (IRQ0 mapped to
1 → Start transmit when nFIFOEMPY = 1 (IRQ0 mapped to nFIFOEMPY)
FIFO_thresh for FIFO_Int_Tx)
Technical support +1.800.704.6079
Table 27
Table 28
TRC103 - 12/15/10
Page 33 of 64