TRC103 RFM, TRC103 Datasheet - Page 16

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

When the TRC103 is in receive mode and MCFG01_Mode [5] bit is set to 1, all of the blocks described above are
enabled. In a normal communication frame, the data stream is comprised of preamble bytes, a start pattern and
the data. Upon receipt of a matching start pattern the receiver recognizes the start of data, strips off the preamble
and start pattern, and stores the data in the FIFO for retrieval by the host microcontroller. This automated data
extraction reduces the loading on the host microcontroller.
The IRQCFG0E_Start_Fill[7] bit determines how the FIFO is filled. If IRQCFG0E_Start_Fill[7] is set to 0, data
only fills the FIFO when a pattern match is detected. Received data bits are shifted into the pattern recognition
block which continuously compares the received data with the contents of the SYNCFG registers. If a match oc-
curs, the pattern matching block output is set for one bit period and the IRQCFG0E_Start_Det[6] bit is also set.
This internal signal can be mapped to the IRQ0 output using interrupt signal mapping. Once a pattern match has
occurred, the pattern recognition block will remain inactive until IRQCFG0E_Start_Det[6] bit is reset.
If IRQCFG0E_Start_Fill[7] is set to 1, FIFO filling is initiated by asserting IRQCFG0E_Start_Det[6]. Once 64
bytes have been written to the FIFO the IRQCFG0D_FIFOFULL[2] signal is set. Data should then be read out. If
no action is taken, the FIFO will overflow and subsequent data will be lost. If this occurs the IRQCFG0D_
FIFO_OVR[0] bit is set to 1. The IRQCFG0D_FIFOFULL[2] signal can be mapped to pin IRQ1 as an interrupt for
a microcontroller if IRQCFG0D_RX_IRQ1[5..4] is set to 01. To recover from an overflow, a 1 must be written to
IRQCFG0D_ FIFO_OVR[0]. This clears the contents of the FIFO, resets all FIFO status flags and re-initiates pat-
tern matching. Pattern matching can also be re-initiated during a FIFO filling sequence by writing a 1 to
IRQCFG0E_Start_Det[6].
The details of the FIFO filling process are shown in Figure 12. As the first byte is written into the FIFO, signal
IRQCFG0D_nFIFOEMPY[1] is set indicating at least one byte is present. The host microcontroller can then read
the contents of the FIFO through the SPI interface. When all data is read from the FIFO, IRQCFG0D_
th
nFIFOEMPY[1] is reset. When the last bit of the 64
byte has been written into the FIFO, signal IRQCFG0D_
FIFOFULL[2] is set. Data must be read before the next byte is received or it will be overwritten.
The IRQCFG0D_nFIFOEMPY[1] signal can be used as an interrupt signal for the host microcontroller by map-
ping to pin IRQ0 if IRQCFG0D_RX_IRQ0[7..6] is set to 10. Alternatively, the WRITE_byte signal may also be
used as an interrupt if IRQCFG0D_RX_IRQ0[7..6] is set to 01.
Demodulation in Buffered data mode occurs in the same way as in Continuous data mode. Received data is di-
rectly read from the FIFO and the DATA and DCLK pins are not used. Data and clock recovery in Buffered data
mode is automatically enabled. DCLK is not externally available.
The pattern recognition block is automatically enabled in buffered mode. The Start Pattern Detect (PATTERN)
signal can be mapped to pin IRQ0. In Buffered data mode RSSI operates the same way as in Continuous data
mode. However, RSSI_IRQ may be mapped to IRQ1 instead of to IRQ0 in continuous mode.
www.RFM.com
E-mail:
[e-mail]
Technical support +1.800.704.6079
Page 16 of 64
©2009-2010 by RF Monolithics, Inc.
TRC103 - 12/15/10