WM8986GECO/V Wolfson Microelectronics, WM8986GECO/V Datasheet - Page 53

• Manufacturer Part Number: WM8986GECO/V
• Description: Audio Amplifiers Class D Headphone DAC + Line Out
• Manufacturer: Wolfson Microelectronics

Specifications of WM8986GECO/V

• Product: Class-D
• Output Power: 40 mW
• Thd Plus Noise: - 86 dB
• Operating Supply Voltage: 1.71 V to 3.6 V, 2.5 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 16 Ohms
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V, 2.5 V
• Output Type: Differential
• Package / Case: QFN-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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Table 32 Audio Interface Control
Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the
device will operate in 24-bit mode.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,
and LRC are outputs. The frequency of BCLK in master mode can be controlled with BCLKDIV. The
frequencies of BCLK and LRC are also controlled by MCLKDIV. The LRC sample rate is set to the
required values by MCLKDIV and the BCLK rate will be set accordingly to provide sufficient BCLKs
for that chosen sample rate. These clocks are divided down versions of master clock.
R4 (04h)
Audio
Interface
Control
REGISTER
ADDRESS
0
2
4:3
6:5
7
8
BIT
MONO
DLRSWAP
FMT
WL
LRP
BCP
LABEL
0
0
10
10
0
0
DEFAULT
Selects between stereo and mono
device operation:
0 = Stereo device operation
1 = Mono device operation. Data
appears in ‘left’ phase of LRC only.
Controls whether DAC data appears in
‘right’ or ‘left’ phases of LRC clock:
0 = DAC left data appear in ‘left’ phase
of LRC and right data in 'right' phase
1 = DAC left data appear in ‘right’ phase
of LRC and right data in 'left' phase
Audio interface Data Format Select:
00 = Right Justified
01 = Left Justified
10 = I
11 = DSP/PCM mode
Word length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits (see note)
LRC clock polarity
0 = normal
1 =inverted
DSP Mode – mode A/B select
0 = MSB is available on 2
edge after LRC rising edge (mode A)
1 = MSB is available on 1
edge after LRC rising edge (mode B)
BCLK polarity
0 = normal
1 = inverted
2
S format
DESCRIPTION
PD, Rev 4.1, June 2009
nd
st
BCLK rising
BCLK rising
WM8986
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