WM8986GECO/V Wolfson Microelectronics, WM8986GECO/V Datasheet - Page 57

• Manufacturer Part Number: WM8986GECO/V
• Description: Audio Amplifiers Class D Headphone DAC + Line Out
• Manufacturer: Wolfson Microelectronics

Specifications of WM8986GECO/V

• Product: Class-D
• Output Power: 40 mW
• Thd Plus Noise: - 86 dB
• Operating Supply Voltage: 1.71 V to 3.6 V, 2.5 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 16 Ohms
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V, 2.5 V
• Output Type: Differential
• Package / Case: QFN-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
Table 48 PLL Frequency Examples
w
MCLK
(MHz)
19.68
19.68
14.4
14.4
19.2
19.2
19.8
19.8
(f1)
12
12
13
13
24
24
26
26
27
27
DESIRED
(SYSCLK)
OUTPUT
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
11.29
11.29
11.29
11.29
11.29
11.29
11.29
11.29
11.29
(MHz)
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
(MHz)
f2
Table 47 PLL Frequency Ratio Control
The PLL performs best when f
are shown in 48.
R36 (24h)
PLL N value
R37 (25h)
PLL K value
1
R38 (26h)
PLL K Value
2
R39 (27h)
PLL K Value
3
REGISTER
ADDRESS
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2 6.947446
2 7.561846
2
2 6.826667
2
2
2 9.178537
2 9.990243
2 9.122909
2 9.929697
2
2
2 6.947446
2 7.561846
2 6.690133
2 7.281778
7.5264
7.5264
8.192
6.272
9.408
10.24
8.192
R
4
3:0
5:0
8:0
8:0
BIT
Ah
7h
8h
6h
7h
6h
6h
9h
9h
9h
9h
9h
7h
8h
6h
7h
6h
7h
PLLPRESCALE
PLLN
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
N
2
LABEL
is around 90MHz. Its stability peaks at N=8. Some example settings
45A1CAh
D3A06Eh
B0AC93h
F28BD4h
3D70A3h
2DB492h
FD809Fh
EE009Eh
F28BD4h
86C226h
8FD525h
6872AFh
86C226h
8FD525h
3126E8h
1F76F7h
3126E8h
482296h
K
REGISTER
R36[3:0]
0
1000
0Ch
093h
0E9h
DEFAULT
XXAh
XX7h
XX8h
XX6h
XX7h
XX6h
XX6h
XX9h
XX9h
XX9h
XX9h
XX9h
XX7h
XX8h
XX6h
XX7h
XX6h
XX7h
N
1 = Divide MCLK by 2 before input
to PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
0 = MCLK input not divided (default)
00Ch
03Ch
01Ah
00Bh
00Ch
03Ch
02Ch
021h
023h
011h
034h
00Fh
03Fh
007h
03Bh
021h
023h
012h
R37
DESCRIPTION
PD, Rev 4.1, June 2009
K REGISTERS
1EAh
0DAh
1BBh
1EAh
0D0h
1D0h
0B8h
0C0h
161h
093h
145h
039h
100h
161h
093h
145h
056h
011h
R38
WM8986
1CAh
1D4h
0AFh
1D4h
026h
0E8h
06Eh
0A3h
0F7h
09Eh
026h
0E8h
093h
125h
092h
125h
096h
09Fh
R39
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