NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 128

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.1.9
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5.4.1.10
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5.4.1.11
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5.4.1.12
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I/O Cycles
For I/O cycles targeting registers specified in the ICH8’s decode ranges, the ICH8
performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision
1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the
ICH8 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.
If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH8
returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with
ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.
Bus Master Cycles
The ICH8 supports Bus Master cycles and requests (using LDRQ#) as defined in the
Low Pin Count Interface Specification, Revision 1.1. The ICH8 has two LDRQ# inputs,
and thus supports two separate bus master devices. It uses the associated START fields
for Bus Master 0 (0010b) or Bus Master 1 (0011b).
The ICH8 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters
should only perform memory read or memory write cycles.
LPC Power Management
CLKRUN# Protocol (Mobile Only)
The CLKRUN# protocol is same as the PCI Local Bus Specification. Stopping the PCI
clock stops the LPC clock.
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive
LDRQ# low or tri-state it. ICH8 shuts off the LDRQ# input buffers. After driving
SUS_STAT# active, the ICH8 drives LFRAME# low, and tri-states (or drive low)
LAD[3:0].
The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. The ICH8 asserts both
SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time
when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not
inconsistent with the LPC LPCPD# protocol.
Configuration and Intel
LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH8
includes several decoders. During configuration, the ICH8 must be programmed with
the same decode ranges as the peripheral. The decoders are programmed via the
Device 31:Function 0 configuration space.
The ICH8 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with
similar characteristics (specifically those with a “Retry Read” feature which is enabled)
to an LPC device if there is an outstanding LPC read cycle towards the same PCI device
or bridge. These cycles are not part of normal system operation, but may be
encountered as part of platform validation testing using custom test fixtures.
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ICH8 Implications
Intel
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Functional Description
ICH8 Family Datasheet