NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 219

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.19.8.3
5.19.8.4
5.19.9
Intel
®
ICH8 Family Datasheet
Device Disconnects
The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision
1.0 describes the details of handling Device Connects in Section 4.2. There are three
general scenarios that are summarized below.
Effect of Resets on Port-Routing Logic
As mentioned above, the Port Routing logic is implemented in the suspend power well
so that remuneration and re-mapping of the USB ports is not required following
entering and exiting a system sleep state in which the core power is turned off.
USB 2.0 Legacy Keyboard Operation
The ICH8 must support the possibility of a keyboard downstream from either a full-
speed/low-speed or a high-speed port. The description of the legacy keyboard support
is unchanged from USB 1.1 (See
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
Suspend Well Reset
Core Well Reset
D3-to-D0 Reset
HCRESET
4. Configure Flag = 1 and a high-speed-capable Device is connected
1. Configure Flag = 0 and the device is disconnected
2. Configure Flag = 1 and a full-speed/low-speed-capable Device is disconnected
3. Configure Flag = 1 and a high-speed-capable Device is disconnected
Reset Event
— In this case, the EHC is the owner of the port before, and remains the owner
— In this case, the UHC is the owner of the port both before and after the
— In this case, the UHC is the owner of the port before the disconnect occurs. The
— In this case, the EHC is the owner of the port before, and remains the owner
bit in the same register, causing the UHC to see a connect event and the EHC to
see an “electrical” disconnect event. The UHCI driver and hardware handle the
connection and initialization process from that point on. The EHCI driver and
hardware handle the perceived disconnect.
after, the connect occurs. The EHCI driver handles the connection and performs
the port reset. After the reset process completes, the EHC hardware has set the
Port Enable bit in the EHC’s PORTSC register. The port is functional at this point.
The UHC continues to see an unconnected port.
disconnect occurs. The EHC (except for the port-routing logic) never sees a
device attached. The UHCI driver handles disconnection process.
disconnect is reported by the UHC and serviced by the associated UHCI driver.
The port-routing logic in the EHC cluster forces the Port Owner bit to 0,
indicating that the EHC owns the unconnected port.
after, the disconnect occurs. The EHCI hardware and driver handle the
disconnection process. The UHC never sees a device attached.
cleared (0)
no effect
no effect
cleared (0)
Effect on Configure Flag
Section
5.18.8).
Effect on Port Owner Bits
set (1)
no effect
no effect
set (1)
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