NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 307

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chipset Configuration Registers
7.1.73
Intel
®
ICH8 Family Datasheet
FDSW—Function Disable SUS Well
Offset Address: 3420h
Default Value:
14:5
6:1
Bit
Bit
15
4
3
2
1
0
7
0
IDE C3 HV IO Biasing Disable (IC3HVBD) — R/W.
0 = IDE HV IO Biasing is always on
1 = IDE HV IO Biasing is disabled on selected pins when in C3.
Reserved
PCI Express* RX Clock Gating Enable (PRXCGEN) — R/W.
0 = AFE Rx clock gating is disabled
1 = AFE Rx clock gating is enabled whenever all PCIe ports Rx are in squelch
DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.
0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled
1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled
PCI Express TX Dynamic Clock Gate Enable — R/W.
0 = PCI Express root port TX Dynamic Clock Gating is Disabled
1 = PCI Express root port TX Dynamic Clock Gating is Enabled
DMI TX Dynamic Clock Gate Enable — R/W.
0 = DMI TX Dynamic Clock Gating is Disabled
1 = DMI TX Dynamic Clock Gating is Enabled
PCI Express Root Port Static Clock Gate Enable — R/W.
0 = PCI Express root port Static Clock Gating is Disabled
1 = PCI Express root port Static Clock Gating is Enabled
Function Disable SUS Well Lockdown (FDSWL)— R/WL
0 = FDSW registers are not locked down
1 = FDSW registers are locked down
NOTE: This bit must be set when Intel
Reserved
LAN Disable — R/WL
0 = LAN is enabled
1 = LAN is Disabled.
If the Function Disable SUS Well Lockdown bit is set, this register is locked.
(ICH8DO and ICH8M-E Only).
0000h
Description
Description
®
Attribute:
Size:
Active Management Technology is enabled
R/W, RO
8-bit
307