NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 325

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.3
9.1.4
Note:
Intel
®
ICH8 Family Datasheet
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h
Default Value:
Lockable:
PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06
Default Value:
Lockable:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Bit
15
14
13
12
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
0 = No action is taken when detecting a parity error.
1 = Enables the ICH8 LPC bridge to respond to parity errors detected on backbone
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity
error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is
0.
0 = Parity Error Not detected.
1 = Parity Error detected.
Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system
error to the internal SERR# logic.
Master Abort Status (RMA) — R/WC.
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the
Received Target Abort (RTA) — R/WC.
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
interface.
backbone.
0007h
No
0210h
Noh
–
07h
–
05h
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W, RO
16-bit
Core
RO, R/WC
16-bit
Core
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