NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 75

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Description
Table 16.
2.13
Table 17.
Intel
®
ICH8 Family Datasheet
Power Management Interface Signals (Sheet 4 of 4)
Processor Interface
Processor Interface Signals (Sheet 1 of 2)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
(Mobile Only) /
(Desktop Only)
STP_CPU#
DPRSLPVR
STP_PCI#
BATLOW#
DPRSTP#
CPUSLP#
GPIO15
GPIO25
GPIO16
A20M#
Name
FERR#
Name
TP0
TP1
Type
Type
O
O
O
O
I
O
O
I
Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock. It is used to support PCI
CLKRUN# protocol. This pin is also used to communicate the host clock
frequency select for ME operation.
If this functionality is not needed, this signal can be configured as a
GPIO.
Stop CPU Clock: This signal is an output to the external clock
generator for it to turn off the processor clock. It is used to support the
C3 state. This pin is also used to communicate the host clock frequency
select for ME operation.
If this functionality is not needed, this signal can be configured as a
GPIO.
Battery Low: This signal is an input from battery to indicate that
there is insufficient power to boot the system. Assertion will prevent
wake from S3–S5 state. This signal can also be enabled to cause an
SMI# when asserted.
Deeper Sleep - Voltage Regulator: This signal is used to lower the
voltage of VRM during the C4 state. When the signal is high, the
voltage regulator outputs the lower “Deeper Sleep” voltage. When low
(default), the voltage regulator outputs the higher “Normal” voltage.
Deeper Stop: This is a copy of the DPRSLPVR and it is active low.
Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE
input being active.
CPU Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during
that time, no snoops occur. The Intel
CPUSLP# signal when going to the S1 state.
Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the ICH8
coprocessor error reporting function is enabled in the OIC.CEN
register (Chipset Configuration Registers:Offset 31FFh: bit 1). If
FERR# is asserted, the ICH8 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the processor unless FERR# is
active. FERR# requires an external weak pull-up to ensure a high
level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the OIC register bit setting.
Description
Description
®
ICH8 can optionally assert the
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