NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 406

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

406
Bit
9
8
7
6
5
4
3
2
1
0
PCI_EXP_EN — R/W.
0 = Disable SCI generation upon PCI_EXP_STS bit being set.
1 = Enables ICH8 to cause an SCI when PCI_EXP_STS bit is set. This is used to
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not
affected by a hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved
TCOSCI_EN — R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
USB5_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB5_STS to generate a wake event.
USB2_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN — R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
SWGPE_EN— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is
written to a 1, hardware will set SWGPE_STS (acts as a level input)
If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1's, an SCI will be generated
If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an
SMI# will be generated
HOT_PLUG_EN — R/W.
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1 = Enables the ICH8 to cause an SCI when the HOT_PLUG_STS bit is set. This is
THRM_EN — R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set
allow the PCI Express* ports, including the link to the (G)MCH, to cause an SCI
due to wake/PME events.
used to allow the PCI Express ports to cause an SCI due to hot-plug events.
the THRM_STS bit and generate a power management event (SCI or SMI).
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet