NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 207

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.18.4.4
5.18.4.5
5.18.4.6
5.18.4.7
5.18.5
5.18.6
5.18.6.1
Intel
®
ICH8 Family Datasheet
Address Fields
Function endpoints are addressed using the function address field and the endpoint
field. Full details on this are given in the Universal Serial Bus Specification, Revision
2.0, in Section 8.3.2.
Frame Number Field
The frame number field is an 11-bit field that is incremented by the host on a per frame
basis. The frame number field rolls over upon reaching its maximum value of 7FFh, and
is sent only for SOF tokens at the start of each frame.
Data Field
The data field may range from 0 to 1023 bytes and must be an integral numbers of
bytes. Data bits within each byte are shifted out LSB first.
Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context,
these fields are considered to be protected fields. Full details on this are given in the
Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5.
Packet Formats
The USB protocol calls out several packet types: token, data, and handshake packets.
Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in
section 8.4.
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution
of transactions in the schedule, and those resulting from an ICH8 operation error. All
transaction-based sources can be masked by software through the ICH8’s Interrupt
Enable register. Additionally, individual transfer descriptors can be marked to generate
an interrupt on completion.
When the ICH8 drives an interrupt for USB, it internally drives the PIRQA# pin for USB
function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC#
pin for USB function #2, until all sources of the interrupt are cleared. In order to
accommodate some operating systems, the Interrupt Pin register must contain a
different value for each function of this new multi-function device.
Transaction-Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction
in the frame has been written back to host memory. This assures that software can
safely process through (Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-Out
A CRC/Time-Out error occurs when a packet transmitted from the ICH8 to a USB device
or a packet transmitted from a USB device to the ICH8 generates a CRC error. The ICH8
is informed of this event by a time-out from the USB device or by the ICH8’s CRC
checker generating an error on reception of the packet. Additionally, a USB bus time-
out occurs when USB devices do not respond to a transaction phase within 19-bit times
of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement.
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