NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 572

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.16
14.1.17
572
USB_RELNUM—Serial Bus Release Number Register
(USB—D29:F0/F1/F2, D26:F0/F1)
Address Offset:
Default Value:
USB_LEGKEY—USB Legacy Keyboard/Mouse Control
Register (USB—D29:F0/F1/F2, D26:F0/F1)
Address Offset:
Default Value:
This register is implemented separately in each of the USB UHCI functions. However,
the enable and status bits for the trapping logic are OR’d and shared, respectively,
since their functionality is not specific to any one host controller.
7:0
Bit
Bit
15
14
13
12
11
Serial Bus Release Number — RO.
10h = USB controller supports the USB Specification, Release 1.0.
SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if
the event occurred. Note that even if the corresponding enable bit is not set in bit 7,
then this bit will still be active. It is up to the SMM code to use the enable bit to
determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred
Reserved
PCI Interrupt Enable (USBPIRQEN) — R/W. This bit is used to prevent the USB
controller from generating an interrupt due to transactions on its ports. Note that, when
disabled, it will probably be configured to generate an SMI using bit 4 of this register.
Default to 1 for compatibility with older USB software.
0 = Disable
1 = Enable
SMI Caused by USB Interrupt (SMIBYUSB) — RO. This bit indicates if an interrupt
event occurred from this controller. The interrupt from the controller is taken before the
enable in bit 13 has any effect to create this read-only bit. Note that even if the
corresponding enable bit is not set in Bit 4, this bit may still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software should clear the interrupts via the USB controllers. Writing a 1 to this bit
1 = Event Occurred.
SMI Caused by Port 64 Write (TRAPBY64W) — R/WC. This bit indicates if the event
occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will
still be active. It is up to the SMM code to use the enable bit to determine the exact
cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h
writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
will have no effect.
60h
10h
C0h
2000h
–
C1h
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W, R/WC, RO
16 bits
UHCI Controllers Registers
Intel
®
ICH8 Family Datasheet