NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 415

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.3.22
Intel
®
ICH8 Family Datasheet
C5_RES— C5 Residency Register (Mobile Only)
I/O Address:
Default Value
Lockable:
Power Well:
Software may only write this register during system initialization to set the state of the
C5_RESIDENCY_MODE bit. It must not be written while the timer is in use.
31:24
23:0
Bit
Reserved
C5_RESIDENCY — RO. The value in this field increments at the same rate as the
Power Management Timer. If the C5_RESEDENCY_MODE bit is clear, this field
automatically resets to 0 at the point when the Lvl5 or Lvl6 read occurs. If the
C5_RESIDENCY_MODE bit is set, the register does not reset when the Lvl5 or Lvl6 read
occurs. In either mode, it increments while STP_CPU# is active (i.e., the processor is in
C3/C4/C5/C6 state). This field will roll over in the same way as the PM Timer, however
the most significant bit is NOT sticky.
Software is responsible for reading this field before performing the Lvl5/6 transition.
Software must also check for rollover if the maximum time in C5/C6 could be
exceeded.
NOTE: Hardware reset is the only reset of this counter field.
PMBASE +58h
00000000h
No
Core
Description
Attribute:
Size:
Usage:
R/W/RO
32-bit
ACPI/Legacy
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