NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 372

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6.2.2
372
RTC_REGB—Register B (General Configuration)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
Bit
7
6
5
4
3
2
1
0
Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not
affected by RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update cycles will not occur until
NOTE: This bit should be set then cleared early in BIOS POST after each powerup
Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on
any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register
Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any
other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the
Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but
not on any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
Square Wave Enable (SQWE) — R/W. This bit serves no function in the ICH8. It is
left in this register bank to provide compatibility with the Motorola 146818B. The ICH8
has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.
Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation.
This bit is not affected by RSMRST# nor any other reset signal.
0 = BCD
1 = Binary
Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is
not affected by RSMRST# nor any other reset signal.
0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and
1 = Twenty-four hour mode.
Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per
year. The days for the hour adjustment are those specified in United States federal law
as of 1987, which is different than previous years. This bit is not affected by RSMRST#
nor any other reset signal.
0 = Daylight Savings Time updates do not occur.
1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to
SET is returned to 0. When set is one, the BIOS may initialize time and calendar
bytes safely.
A.
update cycle. An alarm can occur once a second, one an hour, once a day, or one a
month.
PM as one.
3:00:00 AM.
b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it
is changed to 1:00:00 AM. The time must increment normally for at least two
update cycles (seconds) previous to these conditions for the time change to occur
properly.
directly after coin-cell battery insertion.
0Bh
U0U00UUU (U: Undefined)
No
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Intel
RTC
R/W
8-bit
®
ICH8 Family Datasheet