NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 162

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.13.3
s
Table 64.
5.13.4
162
System Power Planes
The system has several independent power planes, as described in
when a particular power plane is shut off, it should go to a 0 V level.
System Power Plane
SMI#/SCI Generation
On any SMI# event taking place, ICH8 asserts SMI# to the processor, which causes it
to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is
set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI#
is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see
sources are removed.
Table 65
be programmed to cause either an SMI# or SCI. The usage of the event for SCI
(instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI
source has a corresponding enable and status bit.
DEVICE[n]
Controller
MEMORY
Plane
MAIN
CPU
Link
shows which events can cause an SMI# and SCI. Note that some events can
Controlled
SLP_S3#
SLP_S3#
SLP_S4#
SLP_S5#
SLP_M#
signal
signal
signal
signal
GPIO
By
Section
The SLP_S3# signal can be used to cut the power to the processor
completely. The DPRSLPVR support allows lowering the processor’s
voltage during the C4 state.
When SLP_S3# goes active, power can be shut off to any circuit
not required to wake the system from the S3 state. Since the S3
state requires that the memory context be preserved, power must
be retained to the main memory.
The processor, devices on the PCI bus, LPC I/F, and graphics will
typically be shut off when the Main power plane is shut, although
there may be small subsections powered.
When the SLP_S4# goes active, power can be shut off to any
circuit not required to wake the system from the S4. Since the
memory context does not need to be preserved in the S4 state,
the power to the memory can also be shut down.
When SLP_S5# goes active, power can be shut to any circuit not
required to wake the system from the S5 state. Since the memory
context does not need to be preserved in the S5 state, the power
to the memory can also be shut.
This pin is asserted when the manageability platform goes to MOff.
Depending on the platform, this pin may be used to control the
(G)MCH, ICH8 controller link power planes, the clock chip power,
and the SPI flash power.
Individual subsystems may have their own power plane. For
example, GPIO signals may be used to control the power to disk
drives, audio amplifiers, or the display screen.
9.1.3). The interrupt remains asserted until all SCI
Description
Intel
Table
®
Functional Description
ICH8 Family Datasheet
64. Note that