A3PE-BRD600-SKT Actel, A3PE-BRD600-SKT Datasheet - Page 71

• Manufacturer Part Number: A3PE-BRD600-SKT
• Description: MCU, MPU & DSP Development Tools ProASIC3/E Starter Kit
• Manufacturer: Actel

Specifications of A3PE-BRD600-SKT

• Processor To Be Evaluated: ProASIC3/E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PQ208 Package Connections for A3PE600 and
A3P250 Devices
ProASIC3/E Starter Kit User’s Guide and Tutorial
Due to the comprehensive and flexible nature of ProASIC3 device user I/Os, a naming scheme is used to show the
details of the I/O. The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for
differential I/Os.
Figure A-1 on page 72
provide package connections for the A3P250 and A3E600 devices. Pinouts for other devices in the PQ208 family may
be found on the Actel website:
These datasheets are included on the ProASIC3 and ProASIC3E Starter Kit CD. However, the website should always
be referenced for access to the most recent datasheet.
I/O Nomenclature
Gmn is only used for I/Os that also have CCC access – i.e., global pins.
G = Global
m = Global pin location associated with each CCC on the device: A (northwest corner), B
n = Global input MUX and pin number of the associated Global location m, either A0, A1,A2,
u = I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise
x
w = D (Differential Pair) or P (Pair) or S (Single-Ended). D (Differential Pair) if both members
B = Bank
y
= P (Positive) or N (Negative) for differential pairs, or S (Single-Ended) for the I/O that
= Bank number [0..3] for ProASIC3 and [0..7] for ProASIC3E. Bank number starting at 0
(northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west
middle)
B0, B1, B2, C0, C1, or C2
direction
support single-ended and voltage-referenced I/O standards only
of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P
(Pair) if both members of the pair are bonded out but do not meet the adjacency
requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D)
pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency
does not meet the requirements for a true differential pair.
from the northwest I/O bank in a clockwise direction
ProASIC3 Flash Family FPGAs datasheet at
ProASIC3E Flash Family FPGAs datasheet at
and
= Gmn/IOuxwBy
Table A-1 on page 72
are extracted from the ProASIC3 and ProASIC3E datasheets and
www.actel.com/documents/PA3_DS.pdf
www.actel.com/documents/PA3E_DS.pdf
A
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