ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet
ADC1210S065HN/C1:5
Specifications of ADC1210S065HN/C1:5
ADC1210S065HN,518
ADC1210S065HN,518
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ADC1210S065HN/C1:5 Summary of contents
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ADC1210S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 2 — 23 December 2010 1. General description The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s ADC1210S125HN/C1 125 ADC1210S105HN/C1 105 ADC1210S080HN/C1 80 ADC1210S065HN/ Block diagram INP INM Fig 1. Block diagram ADC1210S_SER Product data sheet Single 12-bit ADC; CMOS or LVDS DDR digital outputs Name Description HVQFN40 plastic thermal enhanced very thin quad flat package; ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area REFB 1 REFT 2 3 AGND 4 VCM VDDA 5 ADC1210S HVQFN40 AGND 6 INM 7 8 INP 9 AGND VDDA 10 Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected 6.2 Pin description Table 2. Symbol REFB REFT ...
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... NXP Semiconductors Table 2. Symbol D11 D10 n.c. n.c. DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Symbol D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P n.c. ADC1210S_SER Product data sheet Single 12-bit ADC ...
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... NXP Semiconductors Table 3. Symbol n.c. DAVM DAVP [1] Pins and pins are the same for both CMOS and LVDS DDR outputs (see [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter Supplies V analog supply voltage DDA V output supply voltage DDO I analog supply current DDA I output supply current DDO P power dissipation Clock inputs: pins CLKP and CLKM Low-Voltage Positive Emitter-Coupled Logic (LVPECL) V differential clock input voltage ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Digital outputs, CMOS mode: pins D11 to D0, OTR, DAV Output levels DDO V LOW-level output voltage OL V HIGH-level output voltage OH C output capacitance O Output levels 1.8 V DDO V LOW-level output voltage OL V HIGH-level output voltage OH Digital outputs, LVDS mode: pins D11P to D0P, D11M to D0M, DAVP and DAVM ...
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Dynamic characteristics 10.1 Dynamic characteristics [1] Table 7. Dynamic characteristics Symbol Parameter Conditions Analog signal processing second harmonic MHz 2H i level MHz MHz 170 ...
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Table 7. Dynamic characteristics …continued Symbol Parameter Conditions IMD Intermodulation MHz i distortion MHz MHz 170 MHz i [1] Typical values measured ...
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Table 8. Clock input and digital output timing characteristics Symbol Parameter Conditions LVDS DDR mode timing output: pins D10_D11_P to D0_D1_P, D10_D11_M to D0_D1_M, DAVP and DAVM t propagation DATA PD delay DAV t set-up time su t hold time ...
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... NXP Semiconductors Fig Fig 5. ADC1210S_SER Product data sheet Single 12-bit ADC; CMOS or LVDS DDR digital outputs d(s) t clk CLKP CLKM − 14) DATA DAV t CMOS mode and clock timing d(s) t clk CLKP CLKM − 14 DAVP DAVM t clk LDVS DDR mode and clock timing All information provided in this document is subject to legal disclaimers. Rev. 2 — ...
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... NXP Semiconductors 10.3 SPI timings Table 9. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V values are across the full temperature range T Fig 6. ADC1210S_SER Product data sheet Single 12-bit ADC; CMOS or LVDS DDR digital outputs [1] SPI timings characteristics Parameter SCLK pulse width ...
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... NXP Semiconductors 10.4 Typical characteristics 3.2 C (pF) 3.0 2.8 2.6 2.4 50 150 250 Fig 7. Capacitance as a function of frequency 100 SFDR (dBc 170 MHz (1) DCS on (2) DCS off Fig 9. SFDR as a function of duty cycle () ADC1210S_SER Product data sheet Single 12-bit ADC; CMOS or LVDS DDR digital outputs ...
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... NXP Semiconductors 92 SFDR (dBc) (1) ( 40 C/typical supply voltages (1) T amb = +25 C/typical supply voltages (2) T amb = +90 C/typical supply voltages (3) T amb Fig 11. SFDR as a function of duty cycle () 90 SFDR (dBc 0.5 1.0 1.5 2.0 Fig 13. SFDR as a function of common-mode input voltage (V ...
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... NXP Semiconductors 11. Application information 11.1 Device control The ADC1210S can be controlled via SPI or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins ...
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... NXP Semiconductors 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. ...
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... NXP Semiconductors Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. Input frequency 3 MHz 70 MHz 170 MHz 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 18 ...
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... NXP Semiconductors Fig 19. Dual transformer configuration suitable for a high intermediate frequency 11.3 System reference and power management 11.3.1 Internal/external references The ADC1210S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and ...
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... NXP Semiconductors VREF SENSE Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Selection internal (Figure internal (Figure external (Figure internal via SPI (Figure [1] The voltage on pin VREF is doubled internally to generate the internal reference voltage. ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 21. Internal reference (p-p) full-scale VREF 0.1 μF V SENSE VDDA Fig 23. External reference (p- (p-p) full-scale 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (peak-to-peak (peak-to-peak) (see Table Table 13. INTREF[2:0] 000 001 010 011 ...
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... NXP Semiconductors 11.3.3 Common-mode output voltage (V A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point ...
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... NXP Semiconductors a. Sine clock input c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 k resistors. Fig 28. Equivalent input circuit ADC1210S_SER Product data sheet Single 12-bit ADC ...
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... NXP Semiconductors Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. ...
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... NXP Semiconductors The output resistance is 50 and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see 11 ...
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... NXP Semiconductors Table 14. LVDS_INT_TER[2:0] 000 001 010 011 100 101 110 111 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) can be used to capture the data delivered by the ADC1210S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in Figure 4 11 ...
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... NXP Semiconductors 11.5.7 Output codes versus input voltage Table 16. INP < 1 1.0000000 0.9995117 0.9990234 0.9985352 0.9980469 .... 0.0009766 0.0004883 0.0000000 +0.0004883 +0.0009766 .... +0.9980469 +0.9985352 +0.9990234 +0.9995117 +1.0000000 > +1 11.6 Serial peripheral interface 11.6.1 Register description The ADC1210S serial interface is a synchronous serial communications port that allows easy interfacing with many commonly-used microprocessors ...
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... NXP Semiconductors Table 18 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows falling edge combination with a rising edge on SCLK determine the start of communications ...
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... NXP Semiconductors Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1210S_SER Product data sheet Single 12-bit ADC; CMOS or LVDS DDR digital outputs CS SDIO (CMOS LVDS DDR) ...
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Register allocation map Table 19. Register allocation map Addr Register name R/W Hex Bit 7 Bit 6 0005 Reset and R/W SW_RST operating mode 0006 Clock R/W - 0008 Internal reference R/W - 0011 Output data R/W - standard ...
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... NXP Semiconductors Table 20. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit Symbol Access 7 SW_RST R RESERVED[2: OP_MODE[1:0] R/W Table 21. Clock control register (address 0006h) bit description Default values are highlighted. Bit Symbol Access SE_SEL R/W ...
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... NXP Semiconductors Table 22. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 23. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit Symbol LVDS_CMOS 3 OUTBUF 2 OUTBUS_SWAP DATA_FORMAT[1:0] ...
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... NXP Semiconductors Table 24. Output clock register (address 0012h) bit description Default values are highlighted. Bit Symbol DAVINV DAVPHASE[2:0] Table 25. Offset register (address 0013h) bit description Default values are highlighted. Bit Symbol DIG_OFFSET[5:0] Table 26. Test pattern register 1 (address 0014h) bit description Default values are highlighted. ...
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... NXP Semiconductors Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit Symbol TESTPAT_USER[11:4] Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted. Bit Symbol TESTPAT_USER[3: Table 29. Fast OTR register (address 0017h) bit description Default values are highlighted. ...
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... NXP Semiconductors Table 31. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol Access DAVI_x2_EN R DAVI[1:0] R/W 2 DATAI_x2_EN R DATAI[1:0] R/W Table 32. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted. Bit Symbol BIT_BYTE_WISE LVDS_INT_TER[2:0] ...
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... NXP Semiconductors 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area terminal 1 40 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Revision history Table 33. Revision history Document ID Release date ADC1210S_SER v.2 20101223 Modifications: ADC1210S_SER_1 20100409 ADC1210S_SER Product data sheet Single 12-bit ADC; CMOS or LVDS DDR digital outputs Data sheet status Product data sheet • Data sheet status changed from Preliminary to Product. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Single 12-bit ADC; CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.2 Clock and digital output timing . . . . . . . . . . . . . 9 10 ...